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研究生:賴聰勝
研究生(外文):Tsung-Sheng Lai
論文名稱:局部分群演算法用以合成低功率預先計算型內容可定址記憶體上的低成本參數擷取器
論文名稱(外文):Local Grouping Algorithm for Synthesizing Low-Cost Parameter Extractor of Low-Power Pre-computation-Based Content Addressable Memory
指導教授:賴飛羆賴飛羆引用關係
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:資訊工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:66
中文關鍵詞:內容可定址記憶體預先計算低功率低成本合成演算法
外文關鍵詞:content addressable memory (CAM)pre-computationlow powerlow costsynthesis algorithm
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因為內容可定址記憶體的高速特性,使得它在許多需要高速的設備中扮演著重要的角色,但是它的耗電量也非常的高。在這篇論文中我們提出一個合成演算法用來合成低功率預先計算型內容可定址記憶體上的參數擷取器,使得資料能夠被均勻的映射到每個參數,而且硬體的成本也較少。此外我們也提出一個方法去減少當一些資料在區塊中大部分是相同時,對參數擷取器所帶來的影響。實驗結果顯示,當和Gate-Block Selection演算法比較時,我們的方法可以減少58.88%的功率消耗,也可以省下0.53%的CMOS電晶體數目。如果用我們提出的捨去及交錯法去改善Gate-Block Selection演算法時,我們的方法仍然可以減少13%的功率消耗。
Content addressable memory (CAM) plays an important role on the performance of some devices due to the high speed of CAM. But the power consumption of CAM is also high. In this work, we propose a synthesis algorithm to synthesize the parameter extractor for low-power pre-computation-base CAM (PB-CAM) such that the data can be mapped to parameters uniformly and the cost of the parameter extractor can also be lower. Moreover, we also propose a method to reduce the impact on mapping data to parameters when most data are identical in some data blocks. In the experimental results, the average reduction of the power consumption can achieve 58.88% and the number of CMOS transistors can save 0.53% when compared with Gate-Block Selection algorithm. If the Gate-Block Selection algorithm is also enhanced by our proposed discard and interlaced method (DAI method) then the power consumption can still be reduced by 13%.
口試委員會審定書 i
誌謝 ii
摘要 iii
Abstract iv
Contents v
List of Figures vii
List of Tables ix
Chapter 1 Introduction 1
1.1 Power Dissipation in CMOS VLSI Circuit 1
1.1.1 Switching Power Dissipation 2
1.1.2 Short-Circuit Power Dissipation 2
1.1.3 Leakage Power Dissipation 3
1.2 Concept of Content Addressable Memory 4
1.2.1 Content Addressable Memory 4
1.2.2 Applications of Content Addressable Memory 5
1.2.3 CAM Cell 6
1.2.4 Write Operation of a CAM Cell 7
1.2.5 Read Operation of a CAM Cell 9
1.2.6 Search Operation of a CAM Cell 10
1.2.7 Match Line Structure 11
Chapter 2 Related Work 14
2.1 Selective Pre-charge Scheme 16
2.2 Pre-computation Scheme 17
2.2.1 Ones Count Scheme 18
2.2.2 Block-XOR Scheme 21
2.2.3 Gate-Block Selection Algorithm 22
2.3 Motivation and Objective 25
Chapter 3 Proposed Approach 26
3.1 The Benefit of Distributing the Data Uniformly 26
3.2 Local Grouping Algorithm 28
3.2.1 Definition of the Variables 28
3.2.2 Top Level of Local Grouping Algorithm 29
3.2.3 Grouping Function 31
3.2.4 Find Gate Function 36
3.2.5 Demonstration of Local Grouping Algorithm 40
3.2.6 Time Complexity of Local Grouping Algorithm 43
3.3 Discard and Interlaced Method 45
Chapter 4 Experimental Results 48
4.1 Experimental Environment 48
4.2 Results 52
4.2.1 Experimental Results of Random Data 52
4.2.2 Experimental Results of MiBench 56
Chapter 5 Conclusion 63
References 64
[1]A. P. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, Apr. 1995.
[2]A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, 1 ed. Norwell, MA and AH Dordrecht, The Netherlands: Kluwer Academic Publishers, 1995.
[3]N. S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. S. Hu, et al., "Leakage current: Moore''s law meets static power," Computer, vol. 36, no. 12, pp. 68-75, Dec. 2003.
[4]L. T. Clark, C. Byungwoo, and M. Wilkerson, "Reducing translation lookaside buffer active power," in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 10-13.
[5]V. Chaudhary, T. H. Chen, F. Sheerin, and L. T. Clark, "Critical race-free low-power nand match line content addressable memory tagged cache memory," IET Computers & Digital Techniques, vol. 2, no. 1, pp. 40-44, Jan. 2008.
[6]C.-C. Wu, S.-H. Wen, N.-F. Huang, and C.-N. Kao, "A pattern matching coprocessor for deep and large signature set in network security system," in IEEE Global Telecommunications Conference (GLOBECOM), 2005, p. 5.
[7]K. Pagiamtzis and A. Sheikholeslami, "Content-addressable memory (CAM) circuits and architectures: a tutorial and survey," IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 712-727, Mar. 2006.
[8]K. J. Schultz, "Content-addressable memory core cells: a survey," Integration, the VLSI Journal vol. 23, no. 2, pp. 171-188, Nov. 1997.
[9]G. Kasai, Y. Takarabe, K. Furumi, and M. Yoneda, "200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme," in Proceedings of the IEEE Custom Integrated Circuits Conference, 2003, pp. 387-390.
[10]I. Arsovski, T. Chandler, and A. Sheikholeslami, "A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme," IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 155-158, Jan. 2003.
[11]I. Arsovski and A. Sheikholeslami, "A current-saving match-line sensing scheme for content-addressable memories," in IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, 2003, pp. 304-494 vol.1.
[12]I. Arsovski and A. Sheikholeslami, "A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories," IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1958-1966, Nov. 2003.
[13]K. Pagiamtzis and A. Sheikholeslami, "A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme," IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1512-1519, Sep. 2004.
[14]J.-H. Lee, G.-h. Park, S.-B. Park, and S.-D. Kim, "A selective filter-bank TLB system [embedded processor MMU for low power]," in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 312-317.
[15]P. Echeverria, J. L. Ayala, and M. Lopez-Vallejo, "A banked precomputation-based CAM architecture for low-power storage-demanding applications," in IEEE Mediterranean Electrotechnical Conference (MELECON), 2006, pp. 57-60.
[16]S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, "A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router," IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 853-861, Apr. 2005.
[17]K. Cheong, Q. Shaolei, and A. Mason, "A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead," in Proceedings of the International Symposium on Circuits and Systems (ISCAS), 2004, pp. II-753-6 Vol.2.
[18]C. A. Zukowski and S.-Y. Wang, "Use of selective precharge for low-power content-addressable memories," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 1997, pp. 1788-1791 vol.3.
[19]C.-S. Lin, J.-C. Chang, and B.-D. Liu, "A low-power precomputation-based fully parallel content-addressable memory," IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 654-662, Apr. 2003.
[20]S.-J. Ruan, C.-Y. Wu, and J.-Y. Hsieh, "Low Power Design of Precomputation-Based Content-Addressable Memory," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 3, pp. 331-335, Mar. 2008.
[21]C.-Y. Wu, S.-f. Ruan, C.-K. Cheng, and M.-B. Lin, "A new Block-XOR precomputation-based CAM design for low-power embedded system," in IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2005, pp. 1-4.
[22]J.-Y. Hsieh and S.-J. Ruan, "Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm," in Asia and South Pacific Design Automation Conference (ASPDAC), 2008, pp. 316-321.
[23]Standard deviation. Available: http://en.wikipedia.org/wiki/Standard_deviation
[24]M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, "MiBench: A free, commercially representative embedded benchmark suite," in IEEE International Workshop on Workload Characterization (WWC-4), 2001, pp. 3-14.
[25]SimpleScalar LLC. Available: http://www.simplescalar.com/
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