跳到主要內容

臺灣博碩士論文加值系統

(44.210.99.209) 您好!臺灣時間:2024/04/15 16:15
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:吳新傳
研究生(外文):Xin-Chuan Wu
論文名稱:數位訊號處理器系統層級功率評估
論文名稱(外文):System-level Power Estimation for Digital Signal Processor
指導教授:楊佳玲楊佳玲引用關係
指導教授(外文):Chia-Lin Yang
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:資訊工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:50
中文關鍵詞:指令層級功率估測超長指令位訊號處理
外文關鍵詞:Instruction-level power estimationVLIWdigital signal processor
相關次數:
  • 被引用被引用:0
  • 點閱點閱:193
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在本論文中,我們提出一個指令層級功率估測(Instruction-level power estimation)方法來估算當軟體在嵌入式超長指令字(VLIW)數位訊號處理器(digital signal processor)的耗電量。指令層級功率估測被廣泛運用於軟體優化,其速度比電路層級與邏輯閘層級模擬快數個數量級,而估測誤差率約在10-20%。這份研究顯示將此方法應用於嵌入式超長指令字數位訊號處理器,模擬時間可由數十分鐘縮短至數秒鐘,而誤差約在4-14%。為了估測目標數位訊號處理器執行一程式時的耗電量,我們將目標數位訊號處理器分為三個主要的部分,分別為數位訊號處理器核心,資料記憶體,以及其他耗電量固定的元件。針對數位訊號處理器核心,根據其硬體使用方法,可將之分為共享硬體資源以及獨立硬體資源,而我們分別詳細的描述其耗電情形。針對資料記憶體,兩個主要因素會影響其耗電量:(1) 讀寫動作的次數 (2) 每一次讀寫動作的耗電量。我們提出一個指令層級功率評估方式適用於超長指令字數位訊號處理器,這是考慮記憶體存取以及可變長度指令技術的評估方法。在我們的實驗中,我們所提出的方法降低誤差使得估測最大誤差在4%以內,而額外的模擬負擔為可忽略的。
In this thesis, we present an improved instruction-level power estimation tool to evaluate the power consumption associated with a software code for an embedded VLIW digital signal processor (DSP). Instruction-level power estimation is widely used in software optimizations, of which the speed is order of magnitude faster than circuit- and gate-level simulations and the estimation error is within 10-20%. This work presents its application on an embedded VLIW DSP. The simulation time is reduced from tens of minutes for a kernel-level task to only few seconds and the estimation error is about 4-14%. To estimate the power consumption of target DSP running a program, we partition a target DSP into three major parts, DSP core, data memory and other components that have fixed power consumption. For DSP core, based on the usage of the hardware resources, it can be separated into shared hardware resources and isolated hardware resources, and we model the power consumption respectively. For data memory, we observe two major factors to affect the power consumption of data memory: (1) the number of read/write operation. (2) the power consumption of each read/write operation. We propose an improved power model for instruction-level power estimation of VLIW DSP, which takes into account the memory accesses and the variable-length instructions that are common in such architectures. In our experiments, the proposed approach reduces the maximum estimation error to only 4% and the simulation overheads are neglectable.
Abstract i
Chapter 1 Introduction 1
1.1 Overview of this Work . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Organization of this Thesis . . . . . . . . . . . . . . . . . . . . 4
Chapter 2 Related Work 5
Chapter 3 Target Architecture 11
Chapter 4 Power Model Methodology and Characterization 16
4.1 Power Model Methodology . . . . . . . . . . . . . . . . . . . . 16
4.1.1 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Power Characterization through Gate-Level Simulation . . . . 22
4.2.1 Power Characterization Methodology . . . . . . . . . . 22
4.2.2 Power Characterization Results . . . . . . . . . . . . . 25
Chapter 5 Experimental Results 36
5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 Trace Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 6 Conclusions 47
Bibliography 48
[1] D. C.-W. Chang, I.-T. Liao, J.-K. Lee, W.-F. Chen, S.-Y. Tseng, and C.-W. Jen. Pac dsp core and application processors. in Proc. ICME, pages 289–292, 2006.
[2] T.-W. Hsieh, P.-C. Hsiao, C.-Y. Liao, H.-C. Hsieh, H.-L. Lin, T.-J. Lin, Y.-H. Chu, , and A.-Y. Wu. Energy-effective design & implementation of an embedded VLIW DSP. in Proc. ISOCC, Nov. 2008.
[3] W.-T. Hsieh. On high-level power modeling approaches for IP-based SOC designs. Ph. D. dissertation, National Central University, 2007.
[4] ITRI. http://www.itri.org.tw/.
[5] B. Klass, D. E. Thomas, H. Schmit, and D. F. Nagle. Modeling interinstruction energy effects in a digital signal processor. in Power-Driven Microarchitecture Workshop, in Conjunction With Int. Symp. Computer Architecture,, June 1998.
[6] P. Landman. High-level power estimation. in Proc. Int. Symp. Low Power Electronics and Design, pages 29–35, 1999.
[7] M.-C. Lee, V. Tiwari, S. Malik, and M. Fujita. Power analysis and minimization techniques for embedded DSP software. IEEE Trans. VLSI Syst., pages 123–135, Mar. 1997.
[8] T.-J. Lin, C.-N. Liu, S.-Y. Tseng, Y.-H. Chu, and A.-Y.Wu. Overview of ITRI PAC project - from VLIW DSP processor to multicore computing platform. in Proc. IEEE Int. Symp. VLSI Design, Automation and Test, Apr. 2008.
[9] E. Macii, M. Pedram, and F. Somenzi. High-level power modeling, estimation and optimization. IEEE Trans. Computer-Aided Design, 17:1061–1079, Nov. 1998.
[10] H. Mehta, R. M. Owens, and M. J. Irwin. Instruction level power profiling. in Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, pages 3326–3329, 1996.
[11] J. T. Russell and M. F. Jacome. Software power estimation and optimization for high performance 32-bit embedded processors. in Proc. Int. Conf. Computer Design, pages 328–333, 1998.
[12] M. Sami, D. Sciuto, C. Silvano, and V. Zaccaria. An instruction-level energy model for embedded VLIW architectures. IEEE Trans. Computer-Aided Design, pages 998–1010, Sep. 2002.
[13] D. Sarta, D. Trifone, and G. Ascia. A data dependent approach to instruction-level power estimation. in Proc. Low Power Design IEEE Alessandro Volta Memorial Workshop, pages 182–190, Mar. 1999.
[14] Synopsys PrimeTime PX. http://www.synopsys.com/.
[15] V. Tiwari and M.-C. Lee. Power analysis of a 32-bit embedded micro-controller. in Proc. Design Automation Conf. Asian and South Pacific, pages 141–148, 1995.
[16] V. Tiwari, S. Malik, and A.Wolfe. Power analysis of embedded software: A first step towards software power minimization. IEEE Trans. VLSI Syst., pages 437–445, Dec. 1994.
[17] V. Tiwari, S. Malik, A. Wolfe, and M.-C. Lee. Instruction-level power analysis and optimization of software. in Proc. Int. Conf. VLSI Design, pages 326–328, 1996.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top