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研究生:陳翊豪
研究生(外文):Yi-Hau Chen
論文名稱:高畫質可調式視訊影像編碼之分析與積體電路架構設計
論文名稱(外文):Analysis and VLSI Architecture of High Definition and Scalable Video Coding Standards
指導教授:陳良基陳良基引用關係
指導教授(外文):Liang-Gee Chen
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:英文
論文頁數:244
中文關鍵詞:高畫質影像可調式影像影像編碼器積體電路
外文關鍵詞:high definitionscalable video codingH.264video encoderVLSI
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  • 點閱點閱:177
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在多媒體的各項應用中,視訊編碼系統因為龐大的資料量總是其中最重要的角色,從過去的 H.261、MPEG-1到目前的H.264/AVC系列,視訊資料的壓縮率有了長足的進步,此外為了針對多媒體裝置越多元化的趨勢和使用者多樣化的要求,視訊編碼系統也將注意力放在了功能性的提供上,可調式視訊編碼標準(Scalable Video Coding)也因此而制定,隨之而來的是更多選擇性的預測工具、新的編碼架構與工具的提出,也讓整體視訊編碼器的運算複雜度或式記憶體需求皆是大幅成長。在本篇論文中,我們首先將探討高解析度的影像編碼器系統,接著是討論可調式視訊編碼系統,最後一部分則是可同時支援高解析度的可調式視訊編碼系統。在每一部分的討論分析中都包含了從演算法的改進、資料重複使用策略到硬體架構設計。
論文的第一部分是高解析度的影像編碼器系統,在此部分我們以H.264/AVC High Profile作為案例研究對象,我們首先討論雙向式畫面預測架構對於視訊編碼器的影響,並針對其運算特性提出了畫面層級的平行編碼架構及相對應的硬體運算排程和硬體架構。在空間性預測上,我們也分析了運算的資料依賴性並對此提出適合硬體運算的演算法,硬體設計上也配合可重組化的硬體架構來實現。
在可調式視訊編碼系統上,我們針對時間、空間以及畫面品質這三種影像功能可調性來討論。對於可隱含時間上可調性的各種多重時間階層的編碼架構進行分析,提出了一個可以找出具有最佳編碼品質的多重時間階層編碼組合的快速演算法;在支援空間可調性的層間預測編碼工具上,在簡化演算法以及新的資料重複使用架構配合下,我們提出了一個硬體花費相對較小的層間殘餘值預測的硬體架構。在畫面品質的可調性上,我們選擇了細部品質可調式編碼來達成,並提出三種可降低系統頻寬的設計技巧來達成。此外,我們也針對移動補償式時間濾波實作了一個可經由硬體重組化來支援MCTF與MCP這兩大類的時間預測架構。
論文的最後一部分主要的目的是結合我們提出的各種設計概念,實作一個可向上支援到HD1080p規格的可調式影像編碼器,並同時支援前述的H.264/AVC High Profile來增進在具體應用上的廣度,此編碼器不僅可提供更好的編碼效率,更可藉由所支援的三種影像可調性來提供影像服務給不同規格的多媒體裝置。讓將來的數位家庭環境不再是夢想。
With the progress in multimedia devices, the trend of video coding not only focuses on compression efficiency but also take video functionality into consideration. In this dissertation, video encoder is classified into two categories, high definition video coder and scalable video coder. Then, the combined high definition scalable video encoder chip is discussed. In each part, the discussion includes algorithm modification, data reuse strategy, and architecture design for memory-related issues, hardware cost and power consumption which are the main evaluated topics for video encoder system.

In the first part dissertation, H.264/AVC high profile is taken as case study for high definition and high quality video. For temporal prediction, we consider Bframe scheme and propose frame-parallel encoding scheme to process B-frames in parallel so that the required system memory bandwidth for temporal prediction can be largely saved. For spatial prediction, the open-loop algorithm is developed and the reconfigurable architecture is designed to achieve high profile and HDTV1080p specification.

In the second part of dissertation, the three video scalability of scalable video coding and their corresponding coding algorithms and architectures are discussed individually. For temporal scalability, first, we propose the fast decision strategy to dynamically find the best GOP size for multi-level coding scheme with almost no computation complexity overhead. Then, we analyze the coding structure and coding performance of open-loop multi-level coding schemes and conventional closed coding schemes, and propose an efficient combined hardware architecture for both MCTF and MCP with computation scalability property. For spatial scalability, to solve the doubled computation complexity from inter-layer residual prediction, we propose an IME-simplified scheme and explore the data reuse scheme in transformed domain to achieve the 40% FME hardware cost reduction. For quality scalability, to reduce the frame-level scan order and enormous system memory bandwidth from FGS, we propose three design techniques and layer-wised architecture to save 88 to 92% system memory bandwidth reduction with low hardware cost.

In the last part of dissertation, we combine the high definition specification from H.264/AVC high profile and the three scalabilities from H.264/AVC scalable extension to provide a general scalable video source for ambient environment which is composed of various display devices of totally different specifications. This chip is implemented on a 16:76mm2 die with UMC 90nm process and dissipates 306/411mW at 120/166MHz for high profile and SVC encoding. Compared to previous baseline encoders, our proposed encoder can save 20% to 30% bit rate in single-layer high profile coding and support temporal, spatial, and quality scalability in SVC profile.
中文目錄
中文摘要 3
第一章 緒論 4
第二章針對雙向式預測的畫面平行運算編碼架構 5
第三章支援H.264/AVC High Profile 空間性預測的演算法及架構設計 6
第四章可變式畫面群組架構的快速預測演算法 7
第五章移動補償式時間濾波之架構設計域移動估計之架構設計 8
第六章針對層間殘餘值預測的分析與架構設計 9
第七章針對細部品質可調式編碼的分析與架構設計 10
第八章支援HDTV1080p 的H.264/AVC High Profile 與Scalable Extension 影像編碼器 11
第九章 總結 12

English Abstract xix
Chap.1 Introduction p.1
Chap.2 Frame-Parallel Design Strategy for High Definition Video Encoder with B-frame p.17
Chap.3 Algorithm and Architecture Design for Intra Prediction in H.264/AVC High Profile p.33
Chap.4 Fast Prediction Algorithm of Adaptive GOP Structure for SVC p.61
Chap.5 Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine 79
Chap.6 Cost-Efficient Residual Prediction VLSI Architecture for H.264/AVCScalable Extension p.115
Chap.7 Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension 129
Chap.8 An H.264/AVC Scalable Extension and High Profile HDTV 1080p Encoder Chip p.149
Chap.9 Conclusion p.179
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