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研究生:陳佳韶
研究生(外文):Chia-Shao Chen
論文名稱:薄膜電晶體液晶顯示器源極驅動IC之輸出偏移電壓可測試設計
論文名稱(外文):A DFT Technique for Output Offset Voltage Testing of TFT-LCD Source Driver IC
指導教授:李建模
指導教授(外文):Chien-Mo Li
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:中文
論文頁數:87
中文關鍵詞:可測試設計偏移電壓測試薄膜電晶體液晶顯示器源極驅動晶片
外文關鍵詞:DFToffset voltagetestingTFT-LCDsource driver
相關次數:
  • 被引用被引用:0
  • 點閱點閱:210
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本論文提出一薄膜電晶體液晶顯示器源級驅動IC之輸出偏移電壓可測試設計。此設計可平行執行晶片上之電壓比較,故測試機台所需之頻道數可大幅度降低。模擬結果顯示輸出偏移電壓量測之最高準確度為0.371mV,此設計可節省上百組I/O腳位與51%之測試時間。可測試設計電路實作於晶片之切割道上,故其對原IC為非侵入式設計,此電路佈局不需耗用任何額外的晶圓面積。
This thesis presents a DFT technique to measure the output offset voltages of TFT-LCD source driver IC. The proposed DFT performs on-chip voltage comparison in parallel so the required number of tester channels is greatly reduced. According to simulation results, the accuracy of output offset voltage measurement is 0.371mV. The proposed technique saves hundreds of I/O pins and reduces the total test time by 51%. The DFT circuitry is implemented on the scribe line so it is non-intrusive to the original design. This DFT layout results in zero area overhead.
摘要 I
Abstract III
目錄 V
圖例 VII
表例 XI
第一章 序論 1
1.1論文動機 1
1.2論文簡介 2
1.3論文貢獻 3
1.4論文組織 4
第二章 論文相關背景 5
2.1薄膜電晶體液晶顯示器之源極驅動IC 5
2.1.1功能與特性 5
2.1.2輸出偏移電壓 10
2.1.3極性倒轉開關 12
2.2相關研究 16
第三章 輸出偏移電壓之測試方法 22
3.1臨界電壓搜尋 22
3.2時間平均量測 26
第四章 IC層級之可測試設計 28
4.1電路設計 28
4.1.1高壓區間電路 32
4.1.2低壓區間電路 38
4.1.3控制訊號波型 51
4.1.4量測與校正模式 56
4.2模擬結果 58
4.3電路佈局 67
4.4測試流程 70
4.5問題與討論 75
第五章 電路板層級之可測試設計 78
5.1電路設計 78
5.2實驗結果 81
第六章 未來展望與結論 84
參考文獻 86
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[National 08] National Semiconductor, “FPD33684 - Low Power, Low EMI, TFT-LCD Column Driver with RSDS Inputs, 64 Grayshades, and 384 Outputs for XGA/SXGA Applications”, http://www.national.com/opf/FP/FPD33684.html
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