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研究生:謝協宏
研究生(外文):Hsieh-Hung Hsieh
論文名稱:近電晶體截止頻率之金氧半導體毫米波積體電路設計與實作
論文名稱(外文):Design and Implementation of CMOS Millimeter-Wave Integrated Circuits near the Transistor Cutoff Frequency
指導教授:呂良鴻
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:英文
論文頁數:126
中文關鍵詞:互補式金氧半導體毫米波低雜訊放大器壓控振盪器注入式鎖定除頻器
外文關鍵詞:CMOSmillimeter wavelow-noise amplifiervoltage-controlled oscillatorinjection-locked frequency divider
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近年來,隨著互補式金氧半導體技術日趨成熟,深次微米製程的電晶體截止頻率及最大振盪頻率已超過100 GHz,因而使射頻積體電路得以朝高頻發展。然而,目前金氧半導體毫米波電路的特性,依然受制於許多製程上先天的缺陷,例如:寄生效應、基板損耗及不足的元件能力。因此,近電晶體截止頻率的金氧半導體電路設計,仍是一深具挑戰的研究課題。

本篇論文,為克服互補式金氧半導體頻率限制,提出了一系列創新的電路架構。在第三章中,藉由使用增益放大的技巧,可使高頻低雜訊放大器的小信號增益獲得改善。在第四章中,基於導納轉換的概念,傳統的電感電容共振腔壓控振盪器將可操作於近電晶體截止頻率範圍。在第五章中,透過採用串聯電感補償技術,除四頻率除頻器的鎖定頻寬能有效增大;不僅如此,由於所提出的除四除頻器,無須串接兩級除二電路,故可降低佈局面積,並減少直流功率的消耗。
Due to recent advances in the fabrication technology, transistors with a cutoff frequency (fT) and a maximum oscillation frequency (fmax) beyond 100 GHz have been commercially available in a deep-submicron CMOS process, motivating RF integrated circuit designs towards higher frequencies. Unfortunately, the development of CMOS millimeter-wave circuits has been long impeded by inherent shortcomings such as parasitic components, substrate losses and inferior device capabilities. It is still a challenging task for the designer to realize CMOS circuits near the transistor cutoff frequency.

In this thesis, to alleviate the frequency limitations imposed on CMOS technologies, novel circuit topologies are developed for millimeter-wave operations. In Chapter 3, a gain-enhancement technique is introduced to the low-noise amplifier (LNA) while the small-signal gain is boosted, facilitating circuit operations at higher frequency bands. In Chapter 4, based on the concept of the admittance transformation, the proposed LC-tank voltage-controlled oscillator (VCO) is capable of sustaining the fundamental oscillation at a frequency close to the fT of the transistor. In Chapter 5, by adopting a series-peaking structure, the locking range of the harmonic injection-locked frequency divider is effectively enhanced while the compact integration and reduced dc power can be exhibited since the cascaded divide-by-two stages are avoided.
Acknowledgement i
Abstract iii
Table of Contents vii
List of Figures xi
List of Tables xvii

Chapter 1 Introduction 1

1.1 Millimeter Waves 1
1.1.1 A Brief History of Millimeter Waves 1
1.1.2 Characteristics of Millimeter Waves 4
1.1.3 Millimeter-Wave Applications 7
1.2 CMOS Millimeter-Wave Integrated Circuits 10
1.2.1 Recent Development 11
1.2.2 Motivation of this Thesis 12
1.3 Organization of this Thesis 13

Chapter 2 CMOS Devices at Millimeter Waves 15

2.1 CMOS Active Devices at Millimeter Waves 15
2.2 CMOS Passive Devices at Millimeter Waves 18
2.2.1 Inductor 19
2.2.2 Capacitor 22

Chapter 3 A CMOS Millimeter-Wave Low-Noise Amplifier 25

3.1 The Common-Gate Transistor with a Gate Inductor 26
3.2 The Proposed Topology of LNA 34
3.2.1 Device Size and Gate Bias 34
3.2.2 Small-Signal Characteristics 36
3.2.3 Linearity 38
3.3 Circuit Implementation 39
3.4 Experimental Results 41
3.5 Summary 43

Chapter 4 A CMOS Millimeter-Wave Voltage-Controlled Oscillator 47

4.1 An Admittance-Transforming Cross-Coupled Pair 48
4.2 The Proposed Topology of VCO 55
4.3 Circuit Implementation 59
4.4 Experimental Results 63
4.5 Summary 65

Chapter 5 A CMOS Millimeter-Wave Harmonic Injection-Locked Frequency Divider 69

5.1 The Divide-by-Four Direct Injection-Locked Frequency Divider 71
5.1.1 Modeling 71
5.1.2 Free-Running Oscillation 75
5.1.3 Frequency Division 77
5.2 The Proposed Circuit Topology 89
5.2.1 Input Locking Range 90
5.2.2 Phase Noise 98
5.2.3 Design Parameters 99
5.3 Circuit Implementation 101
5.4 Experimental Results 104
5.5 Summary 106

Chapter 6 Conclusion 109

Bibliography 113

Publications 123
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