臺灣博碩士論文加值系統

本論文使用3um LTPS TFT製程設計一個全數位式鎖相迴路，用來產生倍頻的時脈，本鎖相迴路的輸出頻率範圍是0.625MHz~12MHz，倍頻範圍是1~30倍，模擬結果時間解析度粗調是5.6ns，微調是0.25ns，而量測結果粗調的時間解析度為8ns。鎖相迴路在電路的應用上是一個重要的模組，近年來發展的潮流也是朝全數位化發展。全數位化的好處是電路對製程的變異性不敏感、電路更改製程容易等。

The thesis presents an all-digital phase-locked loop (ADPLL) as a clock generator implemented in 3um LTPS TFT process. The output frequency range of the ADPLL is from 0.625MHz to 12MHz, the multiplication factors of the reference clock are 1 to 30, and the time resolution of the coarse-tuning part of the DCO is 5.6 ns and that of the fine-tuning part is 0.25ns by simulation. The measuring result of the time resolution of course-tuning part is 8ns. PLL is an essential module in many applications, and the trend of development of PLL is toward all-digital realization. The nature of digital circuits has high immunity against process deviation and it is easy for circuits to be ported among different processes.

中文摘要 I
Abstract II
圖目錄 VI
表目錄 IX

第一章 簡介 1
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1.1 低溫多晶矽薄膜電晶體介紹 1
1.2 全數位式鎖相迴路 2
1.3 動機 2
1.4 論文架構 3

第二章 低溫多晶矽薄膜電晶體 5
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2.1 低溫多晶矽薄膜電晶體介紹 5
2.2 電晶體特性曲線 6
2.3 電路設計考量 9
2.3.1 臨界電壓變異性( ) 9
2.3.2 自發熱效應(self-heating) 10

第三章 鎖相迴路介紹 11
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3.1 類比式鎖相迴路 11
3.2 數位控制式鎖相迴路 13
3.3 全數位式鎖相迴路 14
3.4 鎖相迴路比較 18

第四章 全數位式鎖相迴路架構 19
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4.1 電路架構 19
4.2 頻率及相位鎖定演算法 22
4.3 穩定度分析 23
4.4 頻率鎖定 24
4.5 相位鎖定 26
4.6 電路規格 27
4.7 行為模擬 27

第五章 電路模組設計 31
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5.1 數位控制震盪器 31
5.2 數位式相位頻率偵測器 36
5.3 計數器 37
5.4 正反器 38
5.5 鎖定偵測器 42
5.6 Mask 44
5.7 增益控制器 45

第六章 量測結果及閉迴路模擬 47
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6.1 數位控制震盪器量測結果 47
6.2 全數位式鎖相迴路模擬結果 53

第七章 結論及展望 58
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7.1 結論 58
7.2 未來展望 59

參考文獻 60

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