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研究生:李政隆
研究生(外文):Cheng-Lung Li
論文名稱:存在於互補式金氧半電感電容式振盪器之相位雜訊對偏壓電流依賴度之分析
論文名稱(外文):Analysis of Phase Noise Dependence on Bias Current in CMOS LC-Tank Oscillators
指導教授:林宗賢林宗賢引用關係
指導教授(外文):Tsung-Hsien Lin
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:160
中文關鍵詞:振盪器元件雜訊相位雜訊
外文關鍵詞:OscillatorDevice NoisePhase Noise
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在無線通訊系統中,本地振盪源扮演了一個很重要的角色。其中本地振盪源通常是由一個頻率合成器所實現,以確保有穩定以及精確的頻率輸出。進一步地,在大部分的應用中,頻率合成器之相位雜訊嚴重地影響了整個傳送接收機之雜訊效能。身為一個在頻率合成器中之重要電路,壓控振盪器的雜訊將主宰在熱雜訊頻帶之相位雜訊。因此,為了使設計者對於相位雜訊有更進一步的理解,更深入的理論定性分析是必要的。

本論文主要研究方向在探討相位雜訊對偏壓電流依賴度之關係。針對一個電感電容式之壓控振盪器,其主宰的雜訊源主要來自電感之等效並聯電阻、閘極之寄生電阻、金氧半電晶體、以及偏壓電路。當相位雜訊被不同之雜訊源所主宰,相位雜訊對偏壓電流依賴度將會有所不同。另外,本論文提出了一個簡潔的相位雜訊公式,用來支持本論文的定性分析。針對一些給定的系統參數,此相位雜訊之公式也可初步預測電感與電晶體所需要的設計參數與尺寸。

相位雜訊對偏壓電流依賴度之分析是以一個5.4兆赫茲的電感電容式之壓控振盪器所實現。經由此顆使用台積電0.18深次微米製程之壓控振盪器,相關量測結果顯示相位雜訊確實與偏壓電流有性質上的關聯。當然,量測結果也將連帶與模擬結果以及理論模型曲線一起比較。最後,包含ESD防護電路,整個晶片所耗面積為1320 x 1190 um^2。
In wireless communication systems, the local oscillator (LO) plays an important role. The local oscillator is usually realized as a frequency synthesizer so as to achieve the stable as well as precise oscillation frequency. Further, phase noise of a frequency synthesizer significantly affects the noise performance of the whole transceiver. In a PLL-based frequency synthesizer, VCO phase noise often dominates PLL phase noise in the 1/f^2 regime. Thus, deeper theoretical analysis is essential to give an objective insight.

In this thesis, the relationship between phase noise and bias current is discussed. Noise contributors in a LC-tank oscillator are primarily composed of inductor noise, gate-resistor noise, noise from cross-coupled transistors, and noise from bias circuitry. In a word, tendencies of phase noise vs. bias current will be different due to different noise dominators. More details are discussed in the thesis.

In addition, a compact phase noise formula in the 1/f^2 regime for single- and double-switching oscillators is proposed to support qualitative analyses of phase noise. For some given system specifications, like phase noise and power consumption, the sizing prediction can be initially obtained by this compact phase noise formula.

These concepts are realized by the design of a 5.4-GHz CMOS LC-tank P-core VCO. Fabricated in TSMC 0.18-um CMOS mixed-signal process, related measured results are compared with simulation results and theoretical modeling curves to make several conclusions. Finally, the chip including ESD-PADs occupies an area of 1320 x 1190 um^2.
Chapter 1 Introduction 1
1.1 Opening Remarks 1
1.2 Device Noise and Spice Model Reliability 2
1.3 Basics of LC-VCOs 3
1.4 Motivation: Phase Noise vs. Bias Current 4
1.5 Thesis Overview 5
Chapter 2 Device Noise Analysis Using SpectreRF 7
2.1 Introduction 7
2.2 Noticeable Spice-modeling Errors in BSIM3 Family 8
2.2.1 Incorrect Transconductance Dependency on Frequency 8
2.2.2 Lack of Gate Resistor 11
2.2.3 No Excess Short-channel Thermal Noise 12
2.2.4 No Channel-induced Gate Noise 17
2.2.5 Lack of Gate-induced Drain Leakage 20
2.2.6 Other Potentially Erroneous Noise Behavior 21
2.3 Device Noise at Different DC Biases 22
2.3.1 Flicker Noise and Channel Thermal Noise in BSIM3 Family 23
2.3.2 NMOS2V and RFNMOS2V 26
2.3.3 PMOS2V and RFPMOS2V 31
2.3.4 Critical Discussion of Noise Dependence on Bias 37
2.3.5 Comparison between N-type and P-type Current Mirrors 43
2.4 Output Current Noise of Two Different Current Sources 47
2.5 Summary of Device Noise Simulation 53
Chapter 3 Basics of LC-tank Oscillators 55
3.1 Introduction 55
3.2 Tank Characteristics in Oscillators 58
3.2.1 MOS Varactor 59
3.2.2 Integrated Inductor 61
3.3 Differences between Single- and Double-switching Oscillators 63
3.3.1 Before Oscillation Start-up 63
3.3.2 Amplitude Concern during Stable Oscillation 65
3.3.3 Equivalent Noise Sources in Oscillators 67
3.3.4 Output DC-Level Consideration 71
3.4 Fundamental Phase Noise Theory in LC-tank Oscillators 72
3.4.1 Introduction to Line Shape of Oscillator Spectrum 72
3.4.2 Linearly Approximate Phase Noise Model 74
3.4.3 Hajimiri’s Phase Noise Model 76
3.4.4 Other Phase Noise Model 80
3.5 Summary of LC-tank Oscillators 81
Chapter 4 Phase Noise Dependence on Bias Current 83
4.1 Introduction 83
4.2 Modeling of Phase Noise vs. Bias Current 85
4.2.1 Inductor Noise 87
4.2.2 Noise from Cross-coupled Transistors and Gate Resistors 87
4.2.3 Bias Current Noise 89
4.2.4 Compact Phase Noise Formula 90
4.3 Phase Noise vs. Bias Current 93
4.3.1 Gate Resistor’s Character 96
4.3.2 With Negligible Bias Current Noise 97
4.3.3 With Large Bias Current Noise 102
4.4 Buffer-Stage Circuits and BALUNs 107
4.4.1 Buffer-Stage Circuits and Off-chip BALUN 107
4.4.2 Noise Consideration 109
4.5 Summary of Phase Noise vs. Bias Current 110
Chapter 5 Experimental Results 113
5.1 Test Environment Setup 113
5.2 Chip Pin Configurations and Printed Circuit Board Design 114
5.2.1 Chip Pin Configurations 114
5.2.2 Printed Circuit Board Design 115
5.3 DC Supply Noise Measurement 117
5.4 Experimental Results 121
5.5 Summary of Measured Results 127
Chapter 6 Conclusions and Future Work 131
6.1 Conclusions 131
6.2 Future Work 132
Appendix A I/V Characteristics of MOSFETs 133
A.1 Derivation of I-V Characteristics with Velocity Saturation 133
A.2 Transconductance Tendency at a Fixed VDS 135
Appendix B SBCM vs. STTA with Different MQU Dimensions 141
B.1 SBCM vs. STTA with Different MQU 141
B.2 Comparison between Two Different STTAs 141
Appendix C PSRR Simulation for STTA- and SBCM-VCOs 145
C.1 Power Supply Rejection 145
C.2 Sensitivity of Oscillation Frequency to Power Supply 147
References 149
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