跳到主要內容

臺灣博碩士論文加值系統

(3.236.23.193) 您好!臺灣時間:2021/07/24 12:30
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:郭平昇
研究生(外文):Ping-Sheng Kuo
論文名稱:矽鍺量子井/量子點元件和馬鞍形電晶體
論文名稱(外文):SiGe Quantum-Well/Quantum-Dot Devices and Saddle FinFETs
指導教授:劉致為
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:139
中文關鍵詞:矽鍺金氧半相斥位障蕭基馬鞍形場效電晶體
外文關鍵詞:SiGeMISrepulsive barrierSchottkysaddle FinFETs
相關次數:
  • 被引用被引用:0
  • 點閱點閱:156
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本論文中,我們研究矽鍺金氧半元件並且分為實驗部分和模擬部分。
首先,因為矽鍺量子點可以束困電洞,我們首次發現矽鍺量子點的金氧半穿隧二極體會有電洞電流阻礙的現象發生。五層自我生成的矽鍺量子點,每層以一層74奈米的矽為間隔,並在最上方蓋一層130奈米的矽。在結構中加入矽鍺量子點可以在價電帶束困電洞並且形成位障來阻擋電洞電流,實驗發現不管是正偏壓或負偏壓電流都被有效降低。
金屬-氧化物-N型鍺結構被製作成光偵測器。我們使用鋁和鉑當電極去研究此光偵測器的傳輸機制。在負偏壓時,鋁電極元件的暗電流是由在空乏區內由於熱產生的少數載子和從鋁穿隧到N型鍺導電帶的電子電流所組成。然而對鉑電極元件而言,由於鉑(5.65電子伏特)相對鋁(4.15電子伏特)具有較高的金屬功函數,所以從金屬穿隧到N型鍺導電帶的電子電流將被大大的降低。
我們製作N型矽/矽鍺/矽量子井的蕭基二極體並利用鉑當電極,我們發現由於矽鍺量子井在價電帶的能帶偏差所引起的電洞累積會縮短空乏區的寬度。在逆偏壓時,空乏區的縮短會增加電容和電流。傳統的電容電壓量測方式不能用來量測矽/矽鍺/矽量子井結構的消基二極體的位障。
第二部分是模擬,分為應用在動態記憶體上的馬鞍形場效電晶體和矽/鍺/矽量子井結構P型場效電晶體。由於矽/鍺/矽量子井結構會導致空乏區的縮短,因此不需要額外的摻雜去防止源極和汲極的貫穿。對50奈米以下的動態記憶體而言,馬鞍形場效電晶體比鰭片場效電晶體擁有較低的漏電和較佳的特性,我們提出新結構和改變摻雜方式去降低漏電和閘極電容。
In this dissertation, the SiGe metal-insulator-semiconductor devices are studied and we divide into the experiment part and the simulation part.
First, the blockage of hole transport due to excess holes in SiGe dots was observed in the metal-oxide-semiconductor tunneling diodes for the first time. The 5 layers of self-assembled SiGe dots are separated by 74 nm Si spacers and capped with a 130nm Si. The incorporation of SiGe dots confines the excess holes in the valence band, and forms a repulsive barrier to reduce the hole transport current at positive and negative gate biases.
A metal/oxide/n-Ge structure has been utilized as a photodetector. We use Al and Pt as the gate electrodes to evaluate the transport mechanism of the MOS detector. At negative gate bias, the dark current of the Al gate detector is composed of the thermal generation of minority carriers in the depletion region and the electron current tunneling from Al to conduction band of the n-type Ge substrate. However, for the Pt gate detector at negative gate bias, the electron tunneling from Pt to conduction band of the n-type Ge is greatly reduced due to the large work function of Pt (5.65 eV) as compared to Al (3.15 eV).
The hole confinement due to the valence band offset of the Si/SiGe/Si quantum well causes the shrinkage of depletion region for the n-type Si/SiGe/Si Schottky barrier diodes with Pt gates. The shrinkage of depletion region at reverse bias increases capacitance and current. The conventional capacitor-voltage method can not be used to measure the barrier height of Si/SiGe/Si quantum well Schottky diodes due to the shrinkage of depletion region.
The second part is the simulation work of saddle FinFETs for DRAM applications and Si/Ge/Si QW pFETs. No punch-through anti-doping is required for the Si/Ge/Si pFETs due to the shrinkage of depletion region. The saddle FinFETs are demonstrated to be more suitable than the bulk FinFETs for sub-50nm DRAM applications. We proposed new structure and optimized the doping profiles in source/drain to reduce the leakage current and word-line capacitance.
List of Figures ΧІІ
List of Tables ΧVIІІ

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Planar Bulk-Si MOSFET Scaling Challenges 3
1.3 General Background for Bulk FinFET 4
1.4 General Background for Ge Quantum Well pFET 6
1.5 Dissertation Organization 8
1.6 Reference 10

Chapter 2 Transport Mechanism of SiGe Dot MOS Tunneling Diodes 14
2.1 Introduction 14
2.2 Device Fabrication 15
2.3 LPD Oxide Deposition 17
2.4 Transport mechanisms of Metal-Oxide-Semiconductor Devices 18 2.4.1 Control p-Si 18
2.4.2 SiGe-dot MOS Devices 23
2.4.3 Results of LPD Oxynitride 28
2.4.4 Low Temperature Results 31
2.5 Conclusion 38
2.6 Reference 38

Chapter 3 Dark current reduction of Ge MOS photodetectors by high work function electrodes
43
3.1 Introduction 43
3.2 Experiment 44
3.3 Results and Disscusion 45
3.4 Conclusion 50
3.5 References 50

Chapter 4 Si/Si0.2Ge0.8/Si Quantum Well Schottky Barrier Diodes 52
4.1 Introduction 52
4.2 Transport Mechanism of Schottky Barrier Diodes 53
4.2.1 Current Analysis of Schottky Barrier Diodes 53
4.2.2 Quantum Transmission Coefficient 57
4.2.3 Transport Equation 59
4.2.4 Thermionic-Emission Theory 61
4.2.5 Tunneling Current 65
4.3 Result and Discussions 66
4.3.1 Device Fabrication 66
4.3.2 C-V Characteristics of Schottky Barrier Diodes 67
4.4.3 I-V Characteristics of Schottky Barrier Diodes 72
4.3.4 Photo Response of Schottky Barrier Diodes 74

4.4 Conclusion 78
4.5 Reference 78

Chapter 5 Simulation Study of Ge Quantum Well pFET 81
5.1 Introduction 81 76
5.1.1 Advantage of Germanium MOSFETs 81 76
5.1.2 Issues Of Bulk Ge MOSFET 82 77
5.2 Device Structure 84
5.3 Models and Parameters of Simulation 86 81
5.3.1 Si/Ge Band Offset and Band-to-Band Parameter 86
5.3.2 Self-Consistent Schrodinger-Poisson Solution 89
5.4 Results and Discussion 91
5.4.1 Substhreshold Slope Modification of pFET 91
5.4.2 Cap Thickness Variation 94
5.4.3 Ge layer Thickness Variation 98
5.5 Conclusion 101
5.6 Reference 101

Chapter 6 Simulation Study of Body-Tied Saddle
FinFETs for Sub-50 nm DRAM Generation 104

6.1 Introduction 104
6.2 Introduction of DRAM 105 112
6.2.1 DRAM Scaling 105
6.2.2 The Reverse Body Bias 107
6.2.3 The Negative Word Line 108
6.3 Model of Band-to-Band Tunneling 109
6.4 Simulation Results and Discussion 113
6.4.1 Device Structure 113
6.4.2 Threshold Voltage Variation with Recess Depth 115
6.4.3 Fin Height and Fin Width Variation 116
6.4.4 DIBL with different Body bias 118
6.4.5 Gate-induced-Drain-Lleakage (GIDL) and junction leakage (JLK) 119
6.4.6 Saddle FinFET v.s bulk FinFET 121
6.4.7 The effect of side gate-to-S/D overlap length 122
6.4.8 Side Wall Oxide 124
6.4.9 Lightly Drain Doping (LDD) 126
6.5 Conclusion 128
6.6 Reference 128

Chapter 7 Summary and Further Work 132
7.1 Summary 132
7.2 Further Work 133
138
Appendix Related Publication 136
[1-1]. L.-P. Chen, Y.-C. Chan, S.-J. Chang, G.-W. Huang and C.-Y. Chang, “Direct Oxidation of Si1- xGe x Layers Using Vacuum-Ultra-Violet Light Radiation in Oxygen,” Jpn. J. Appl. Phys. vol. 37, pp. L122-L124, Feb., 1998.
[1-2]. G. Sun, R. A. Soref and J. B. Khurgin, “Phonon-pumped SiGe-Si interminiband terahertz laser,” IEEE J. Sel. Top. Quantum Electronics. vol. 7, pp. 376-380, Mar./Apr., 2001.
[1-3]. H. Hirayama, M. Hiroi, K. Koyama and T. Tatsumi, “Heterojunction bipolar transistor fabrication using Si1−xGex selective epitaxial growth by gas source silicon molecular beam epitaxy,” Appl. Phys. Lett. vol. 56, issue 26, pp. 2645, June, 1990.
[1-4]. S. J. Xu, S. J. Chua, T. Mei, X. C. Wang, X. H. Zhang, G. Karunasiri, W. J. Fan, C. H. Wang, J. Jiang, S. Wang and X. G. Xie, “Characteristics of InGaAs quantum dot infrared photodetectors,” Appl. Phys. Lett. vol. 73, issue 21, pp. 3153, Nov., 1998.
[1-5]. B. F. Levine, “Quantum-well infrared photodetectors,” J. Appl. Phys. vol. 74, issue 8, pp. R1-R81, Oct. 1993.
[1-6]. T. Fromherz, P. Kruck, M. Helm, G. Bauer, J. F. Nutzel and G. Abstreiter, “Transverse magnetic and transverse electric polarized inter-subband absorption and photoconductivity in p-type SiGe quantum wells,” Appl. Phys. Lett. vol. 68, issue 25, pp. 3611, June, 1996.
[1-7] G. E. Moore, "Cramming more components onto integrated circuits," Electronics, pp. 114–117, Apr. 19, 1965.
[1-8] G. E. Moore, "No exponential is forever: but "Forever" can be delayed!," Proc.
Proceedings of IEEE International Solid-State Circuits Conference. San Francisco,
CA, 2003
[1-9] Woo Oh Chung et al. “A 4-Bit Double SONOS Memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation,“ Symp. VLSI Tech. Dig., pp. 40, 2006.
[1-10] Yong-Sung Kim et al., “Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations,” IEDM Tech. Dig., p. 315, 2005
[1-11] Kinam Kim, “Technology for sub-50nm DRAM and NAND Flash Manufacturing”, Technical Digest IEDM , p.323, 2005
[1-12] Q. Ouyang, X. Chen, S. P. Mudanai, X. Wang, D. L. Kencke, Al F. Tasch, L.
F. Register, and S. K. Banerjee, “A Novel Si/SiGe Heterojunction pMOSFET with
Reduced Short Channel Effects and Enhanced Drive Current,” IEEE Trans. Electron
Devices, vol. 47, no. 10, pp. 1943-1949, Oct. 2000.
[1-13] A. Rahman, A. Ghosh, and M. Lundstrom, “Assessment of Ge n-MOSFET by
Quantum Simulation,” in IEDM Tech. Dig., 2003, pp. 471-474.
[1-14] H. Shang, J. O. Chu, X. Wang, P. M. Mooney, K. Lee, J. Ott, K. Rim, K. Chan,
K.Guarini, M. Ieong, “Channel Design and Mobility Enhancement in Strained
Germanium Buried Channel MOSFETs,” in 2004 Int. Symp. VLSI Tech. Dig., 2004, pp.204-205.
[1-15] K. Rim, J. L. Hoyt, and J. F. Gibbons, “Fabrication and analysis of deep submicron strained-Si n-MOSFETs,” IEEE Trans. Electron Devices, vol. 47, pp. 1406-1415, no. 7, July 2000.
[1-16] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys. vol. 80, issue 4, pp. 2234, Aug. 1996.
[1-17] T. Irisawa, S. Tokumitsu, T. Hattori, K. Nakagawa, S. Koh, and Y. Shiraki, “Ultrahigh room-temperature hole Hall and effective mobility in Si0.3Ge0.7/Ge/Si0.3Ge0.7 heterostructures,” Appl.Phys. Lett. vol. 81, issue 5, pp. 847, July, 2002.

[2-1]. H. Ishikuro, T. Hiramoto, “Quantum mechanical effects in the silicon quantum dot in a single-electron transistor,” Appl. Phys. Lett. vol. 71, issue 25, pp. 3691, Dec. 1997.
[2-2]. R. Apetz, L. Vescan, A. Hartmann, C. Dieker, H. Luth, “Photoluminescence and electroluminescence of SiGe dots fabricated by island growth,” Appl. Phys. Lett. vol. 66, issue 4, pp. 445, Jan., 1995.
[2-3]. H. Sunamura, N. Usami, Y. Shiraki, S. Fukatsu, “Island formation during growth of Ge on Si(100): A study using photoluminescence spectroscopy,” Appl. Phys. Lett. vol. 66, issue 22, pp. 3024, May, 1995.
[2-4]. C.K. Seal, D. Samara, S.K. Banerjee, “Chemical vapor deposition growth and characterization of undoped and doped Ge and Ge1 – xCx quantum dots on Si,” Appl. Phys. Lett. vol. 71, issue 24, pp. 3564, Dec. 1997.
[2-5]. M. Krishnamurthy, B.K. Yang, J.D. Well, C.G. Slough, “Heterogeneous nucleation of coherently strained islands during epitaxial growth of Ge on Si(110),”
Appl. Phys. Lett. vol. 70, issue 1, pp.49, Jan., 1997.
[2-6]. C.S. Ozkan, W.D. Nix, H. Gao, “Strain relaxation and defect formation in heteroepitaxial Si1 – xGex films via surface roughening induced by controlled annealing experiments,” Appl. Phys. Lett. vol. 70, issue 17, pp. 2247, Apr., 1997.
[2-7]. J.D. Weil, X. Deng, M. Krishnamurthy, “Preferential nucleation of Ge islands at self-organized pits formed during the growth of thin Si buffer layers on Si(110),” J. Appl. Phys. vol. 83, issue 1, pp. 212, Jan., 1998.
[2-8]. Y. S. Tang, S. Cai, G. Jin, J. Duan, K.L. Wang, H.M. Soyez, B.S. Dunn, “SiGe quantum dots prepared on an ordered mesoporous silica coated Si substrate,” Appl. Phys. Lett. vol. 71, issue 17, pp. 2448, Oct. 1997.
[2-9]. E.S. Kim, N. Usami, Y. Shiraki, “Control of Ge dots in dimension and position by selective epitaxial growth and their optical properties,” Appl. Phys. Lett. vol. 72, issue 13, pp. 1617, Mar. 1998.
[2-10]. J. Tersoff, C. Terchert, M.G. Lagally, “Self-Organization in Growth of Quantum Dot Superlattices,” Phys. Rev. Lett. vol. 76, issue 10, pp. 1675, 1996.
[2-11]. D. C. Liu, C.P. Lee, “Novel fabrication technique towards quantum dots,” Appl. Phys. Lett. vol. 63, issue 25, pp. 3503, Dec., 1993.
[2-12]. D. Buttard, D. Bellet, G. Dolino, “Thin layers and multilayers of porous silicon: X-ray diffraction investigation,” J. Appl. Phys. vol. 83, issue 11, pp. 5814, June, 1998.
[2-13]. C. W. Liu, M. H. Lee, M.-J. Chen, I. C. Lin, and C-F Lin, “Room-temperature electroluminescence from electron-hole plasmas in the meta-oxide-silicon tunneling diodes,” Appl. Phys. Lett., vol. 76, no. 12, pp. 1516-1518, 2000.
[2-14]. C. W. Liu, W. T. Liu, M. H. Lee, W. S. Kuo, and B. C. Hsu, “A novel photodetector using MOS tunneling structures,” IEEE Electron Device Lett., vol. 21, no. 6, pp. 307-309, 2000.
[2-15]. M. H. Liao, C.-Y. Yu, T.-H. Guo, C.-H. Lin, and C. W. Liu, “Electroluminescence from the Ge quantum dot MOS tunneling diodes,” IEEE Electron Device Lett., vol. 27, no.4, pp. 252-254, 2006.
[2-16]. B.-C. Hsu, S. T. Chang, T.-C. Chen, P.-S. Kuo, P. S. Chen, Z. Pei, and C. W. Liu, “A high efficient 820nm MOS Ge quantum dot photodetector,” IEEE Electron Device Lett., vol. 24, no. 5, pp. 318-320, 2003.
[2-17]. O. G. Schmidt and K. Eberl, “Multiple layers of self-assembled Ge/Si islands:
Photoluminescence, strain fields, material interdiffusion, and island formation,” Physical Review B, vol. 61, no. 20, pp. 13721~13729, 2000.
[2-18]. G. Schmidt and K. Eberl, “Strain and band-edge alignment in single and multiple layers of self-assembled Ge/Si and GeSi/Si islands,” Physical Review B, vol. 62, no. 24, pp. 16715~16720, 2000.
[2-19]. B.-C. Hsu, W. –C. Hua, C.-R. Shie, K.-F. Chen, and C. W. Liu, “Growth and electrical characteristics of liquid-phase deposited SiO2 on Ge,” Electrochem. and Solid-State Lett., 6(2), F9-F11, 2003.
[2-20]. C.-H. Lin, B.-C. Hsu, M. H. Lee, and C.W. Liu, “A comprehensive study of inversion current in MOS tunneling diodes,” IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2125-2130, 2001.
[2-21]. Synopsys Sentaurus.
[2-22]. C.-H. Lin, C.-Y. Yu, P.-S. Kuo, C.-C. Chang, T.-H. Guo, and C. W. Liu, “Delta-doped MOS Ge/Si quantum dot/well infrared photodetector,” Thin Solid Films, vol. 508, pp. 389-392, 2006.

[3-1]. M. Yang, J. Schaub, D. Rogers, M. Ritter, K. Rim, J. Welser, B. Park, “High speed silicon lateral trench detector on SOI substrate,” IEDM Tech. Dig., Dec 2001, pp. 547-550.
[3-2].C. L. Schow, R. Li, J. D. Schaub, J. C. Campbell, “Design and implementation of high-speed planar Si photodiodes fabricated on SOI substrates,” IEEE J. Quantum Electron., vol. 35, pp. 1478-1482, 1999.
[3-3].C. W. Liu, W. T. Liu, M. H. Lee, W. S. Kuo, and B.-C. Hsu, “A novel photodetector using MOS tunneling structures,” IEEE Electron Device Lett., vol. 21, no. 6, pp. 307-309, 2000.
[3-4].M. H. Liao, C.-Y. Yu, T.-H. Guo, C.-H. Lin, and C. W. Liu, “Electroluminescence from the Ge quantum dot MOS tunneling diodes,” IEEE Electron Device Lett., vol. 27, no.4, pp. 252-254, 2006.
[3-5].B.-C. Hsu, S. T. Chang, T.-C. Chen, P.-S. Kuo, P. S. Chen, Z. Pei, and C. W. Liu, “A high efficient 820nm MOS Ge quantum dot photodetector,” IEEE Electron Device Lett., vol. 24, no. 5, pp. 318-320, 2003.
[3-6].B.-C. Hsu, S. T. Chang, C.-R. Shie, C.-C. Lai, P. S. Chen, and C. W. Liu, “High efficient 820nm MOS Ge quantum dot photodetectors for short-reach integrated optical receivers with 1300 nm and 1550 nm sensitivity,” IEDM Tech. Dig., Dec 2002, pp. 91-94.
[3-7].B.-C. Hsu, W. -C. Hua, C.-R. Shie, K.-F. Chen, and C. W. Liu, “Growth and electrical characteristics of liquid-phase deposited SiO2 on Ge,” Electrochem. and Solid-State Lett., 6(2), F9-F11, 2003.
[3-8].B.-C. Hsu, C.W. Liu, W. T. Liu, and C.-H. Lin, “A PMOS tunneling photodetector,” IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1747-1749, 2001.

[4-1]. D. Connelly, C. Faulkner, and D. E. Grupp, “Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate CMOS,” IEEE Trans. Electron Devices, vol. 50, issue 5, pp. 1340-1345, May, 2003.
[4-2]. A. Asenov, M. Jaraiz, S. Roy, G. Roy, F. Adamu-Lema, A. R. Brown, V. Moroz, and R. Gafiteanu, “Integrated atomistic process and device simulation of decananometre MOSFETs,” in Proc. 2002 IEEE SISPAD, pp. 87-90.
[4-3]. S. M. Sze, Physics of Semiconductor Devices (Wiley, New Jersey, 2006).
[4-4]. C. R. Crowell and S. M. Sze, “Current transport in metal-semiconductor barriers,” Solid State Electrons, vol. 9, pp. 1035-1048, 1966.
[4-5]. M. H. Liao, P.-S. Kuo, S.-R. Jan, S. T. Chang, and C. W. Liu, “Strained Pt Schottky diodes on n-type Si and Ge,” Appl. Phys. Lett. vol. 88, issue 14, pp. 143509, Apr. 2006.
[4-6]. E. H. Rhoderick and R. H. Williams, Metal-Semiconductor Contacts, 2nd Ed., Clarendon, Oxford, 1988.
[4-7]. C. R. Crowell and S. M. Sze, “Quantum-Mechanical Reflection of Electrons at Metal-Semiconductor Barriers: Electron Transport in Semiconductor-Metal-Semiconductor Structures,” J. appl. Phys. vol. 37, issue 7, pp. 2683, June, 1966.
[4-8]. C. R. Crowell and S. M. Sze, “Current transport in metal-semiconductor barriers,” Solid State Electrons, vol. 9, pp. 1035-1048, 1966.
[4-9]. H. A. Bethe, “Theory of the Boundary Layer of Crystal Rectifiers,” MIT Radiat. Lab. Rep., pp. 43-12 (1942).
[4-10]. C. R. Crowell, “The Richardson Constant for Thermionic Emission in Schottky Barrier Diodes,” Solid-State Electron., vol. 8, pp. 395, 1965.
[4-11]. Vincent W. L. Chin, John W. V. Storey and M. A. Green, “Characteristics of p-type PtSi Schottky diodes under reverse bias,” J. Appl. Phys. vol. 68, issue 8, pp. 4127-4132, Oct. 1990.
[4-12]. Synopsys Sentaurus.
[4-13]. M. H. Liao, T.-H. Cheng, C. W. Liu, Lingyen Yeh, T.-L. Lee, and M.-S. Liang, “2.0 µm electroluminescence from Si/Si0.2Ge0.8 type II heterojunctions,” J. Appl. Phys., vol. 103, issue 1, pp. 013105, Jan. 2008.
[4-14]. M. G. Ancona, J. B. Boos, N. Papanicolaou, W. Chang, B. R. Bennett and D. Park, “Modeling gate leakage in InAs/AlSb HEMTs,” SISPAD, pp. 295-298, 2003.

[5-1] C. C. Yen, B. J. Chow, F. GAO, S. J. Lee, M. H. Lee, C. –Y. Yu, C. W. Liu, L. J. tang, and T. W. Lee, “Electron Mobility Enhancement Using Ultra thin Pure Ge on Si Substrate,” IEEE Electron Device Lett., vol. 26, no. 10, pp. 761-763, 2005.
[5-2] S. Sze, Physics of Semiconductor Devices, 2nd Ed., New York: Wiley, 1981.
[5-3] M. L. Lee and E. A. Fitzgerald, “Optimized strained Si/ strained Ge dual channel heterostructures for high mobility P- and N- MOSFETs,” IEDM Tech. Dig., pp. 429-432, 2003.
[5-4] H. Shang, J. O. Chu, S. Bedell, E. P. Gusev, P. Jamison, Y. Zhang, J. A. Ott, M. Copel, D. Sadana, K. W. Guarini, and M. Leong, “Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS,” IEDM Tech. Dig., pp.157-160, 2004.
[5-5] A. Satta, T. Janssens, T. Clarysse, E. Simoen, M. Meuris, A. Benedetti, I. Hoflijk, B.De Jaeger, C. Demeurisse, and W. Vandervorst, "P implantation doping of Ge: diffusion, activation, and recrystallization," J. Vac. Sci. Technol. B, vol. 24, no. 1, pp. 494-498, Jan./Feb. 2006.
[5-6] O.J. Gregory, L.A. Pruitt, E.E. Crisman, C. Roberts, and P.J. Stiles, "Native oxides formed on single-crystal germanium by wet chemical reactions," J. Electrochem. Soc., vol. 135, no. 4, pp. 923-929, Apr. 1988.
[5-7] K. Prabhakaran and T. Ogino, "Oxidation of Ge(100) and Ge( 11) surfaces: an UPS and XPS study," Surf Sci., vol. 325, pp. 263-271, Mar. 1995.
[5-8] W.A. Albers, E.W. Valyocsik, and P.V. Mohan, "Tetragonal germanium dioxide layers on germanium," J. Electrochem. Soc., vol. 113, no. 2, pp. 196-198, Feb. 1966.
[5-9] Q. Ouyang, X. Chen, S. P. Mudanai, X. Wang, D. L. Kencke, Al F. Tasch, L. F. Register, and S. K. Banerjee, “ A Novel Si/SiGe Heterojunction pMOSFET with Reduced Short Channel Effects and Enhanced Drive Current,” IEEE Trans. Electron Devices., vol. 47, no. 10, pp. 1943-1949, Oct. 2000.
[5-10] A. Rahman, A. Ghosh, and M. Lundstrom, “Assessment of Ge n-MOSFET by Quantum Simulation,” in IEDM Tech. Dig., 2003, pp. 471-474.
[5-11] H. Shang, J. O. Chu, X. Wang, P. M. Mooney, K. Lee, J. Ott, K. Rim, K. Chan, K.Guarini, M. Ieong, “Channel Design and Mobility Enhancement in Strained Germanium Buried Channel MOSFETs, ” in 2004 Int. Symp. VLSI Tech. Dig., 2004, pp. 204-205.
[5-12] K. Rim, J.L. Hoyt, and J. F. Gibbons, “Fabrication and analysis of deep submicron strained-Si n-MOSFETs,” IEEE Trans. Electron Devices, 2000, vol. 47, pp. 1406-1415, no. 7, July 2000.
[5-13] C. G. Van de Walle and R. M. Martin, “Theoretical calculation of heterojunction discontinuities in the Si/Ge system,” Phys. Rev. B, Condens. Matter, vol. 34, no. 8, pp. 5621-5634, Oct. 1986.
[5-14] Donghyun Kim, Tejas Krishnamohan, Lee Smith, H.-S. Philip Wong, Krishna C. Saraswat, “Band to Band Tunneling Study in High Mobility Materials : III-V, Si, Ge and strained SiGe”, Device Research Conference, 2007 65th Annual, pp.57-58.

[6-1]. J. H. Lee, T. Park, E. Yoon, and Y. J. Park, “Simulation study of a new body-tied FinFETs (Omega MOSFETs) using bulk Si wafers,” in Proc. Si Nanoelectronics Tech. Dig., 2003, pp. 102–103.
[6-2]. Y. -K. Choi, T. –J. King, Chenming Hu, “Nanoscale CMOS spacer FinFET for the terabit era,” IEEE Electron Device Letter, vol.23, issue 1, pp. 25, Jan., 2002.
[6-3]. K.-H. Park, K.-R. Han, Y. M. Kim, and J.-H. Lee, “Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors,” IEEE Electron Device Letter. vol. 27, issue 9, pp. 759-761 Sept., 2006.
[6-4]. R. H. Dennard, “Field-Effect Transistor Memory,” U.S. Patent 3,387,286, 1968.
[6-5]. E. Adler, J. K. DeBrosse, S. F. Geissler, S. J. Holmes, M. D. Jaffe, J. B. Johnson, C. W. Koburger III, J. B. Lasky, B. Lloyd, G. L. Miles, J. S. Nakos, W. P. Noble, Jr., S. H. Voldman, M. Armacost, and R. Ferguson, “The Evolution of IBM CMOS DRAM Technology,” IBM J. Res. & Dev. 39, 167–188 (1995).
[6-6]. K. Kim, C.-G. Hwang, and J. Lee, “DRAM Technology Perspective for Gigabit Era,” IEEE Trans. Electron Devices 45, 598 – 608 (1998).
[6-7]. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions,” IEEE J. Solid-State Circuits SC-9, 256 –268 (1974).
[6-8] L. V. Keldysh, “Behavior of non-metallic crystals in strong electric fields,” Sov. Phys.-JETP, vol. 33, no. 4, pp. 763-770, 1958.
[6-9] L. V. Keldysh, “Influence of the lattice vibrations of a crystal on the production of electron-hole pairs in strong electric fields,” Sov. Phys. -JETP, vol. 34, no. 4, pp. 665-668, 1958.
[6-10] E. O. Kane, “Theory of tunneling,” J. Appl. Phys., vol. 32, no. 1, pp. 83-89, 1961.
[6-11] G. A. M. Hurkx, D. B. M. Klaassen, M. P. G. Knuvers, and F. G. O’Hara, “A new recombination model describing heavy-doping effects and low-temperature behaviour,” in Proc. Int. Electron Device Meeting (Washington, DC), 1989, pp. 307-310.
[6-12] G. A. M. Hurkx, “On the modelling of tunnelling currents in reverse biased
p-n junctions,” Solid-State Elecrron., vol. 32, no. 8, pp. 665- 668, 1989.
[6-13]. K. Okano, et al., “Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length,” International Electron Devices Meeting (IEDM), pp.721-724, Dec. 2005.
[6-14]. G. A. M. Hurkx, D. B. M. Klaassen, and M. P. G. Knuvers, “A new recombination model for device simulation including tunneling,” IEEE Trans. Electron Devices, vol. 39, issue 2, pp. 331-338, Feb. 1992.
[6-15]. L. V. Keldysh, “Behavior of non-metallic crystals in strong electric fields,” Sov. Phys.-JETP, vol. 33, no. 4, pp. 763-770, 1958.
[6-16]. E. O. Kane, “Theory of tunneling,” J. Appl. Phys., vol. 32, issue. 1, pp. 83-89, Jan, 1961.
[6-17]. G. A. M. Hurkx, D. B. M. Klaassen, M. P. G. Knuvers, and F. G. O’Hara, “A new recombination model describing heavy-doping effects and low-temperature behaviour,” in Proc. Int. Electron Device Meeting (Washington, DC), 1989, pp. 307-310.
[6-18]. G. A. M. Hurkx, “On the modelling of tunnelling currents in reverse biased p-n junctions,” Solid-State Elecrron., vol. 32, no. 8, pp. 665-668, 1989.
[6-19]. J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. Divakaruni, Y. Li, and C. J. Radens, “Challenges and future directions for the scaling of dynamic random-access memory (DRAM),” IBM J. Res. & Dev. vol. 46, pp. 187-212, 2002.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top