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研究生:林聖祐
研究生(外文):Sheng-You Lin
論文名稱:全數位展頻時脈產生器
論文名稱(外文):All-Digital Spread Spectrum Clock Generators
指導教授:劉深淵
指導教授(外文):Shen-Iuan Liu
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:94
中文關鍵詞:全數位展頻時脈
外文關鍵詞:All-digitalSpread spectrum clock generator
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In a PC system, the speed of the center process unit (CPU) improves continuously. If the I/O interface is not able to improve simultaneously, the performance of the PC system will be limited. Therefore, high-speed I/O interface are becoming popular. As operating in high data rate, the high-frequency clock causes electromagnetic interference (EMI) which may affect the wireless communication system. Therefore, reduction of unnecessary EMI is a very important issue. Serial AT Attachment (SATA) is one of the most promising technologies providing large bandwidth up to 3Gbps with possible extension to 6Gbps in the near future. In SATA, a spread-spectrum clocking (SSC) technique is specified to reduce the peak EMI emission by spreading the carrier frequency.
In this work, an all-digital spread spectrum clock is proposed for SATA application. The all-digital implemented circuits have the advantage of high portability, small area, high performance in the advanced process, and better integrity in digital system. In the first chip work, a mixed-signal phase/frequency detector is proposed to degrade the quantization noise. The time amplifier is implemented with the phase decision circuit to eliminate the deadzone. The digital controlled oscillator (DCO) resolution enhancement circuit combined with delta-sigma modulator (DSM) is proposed to enhance the resolution of the DCO. With the resolution enhancement circuit, the operation frequency of the DSM is reduced to achieve the same performance. The experimental chip is fabricated in a 0.18um CMOS process. The R.M.S jitter of the output clock is 4ps at 1.5GHz. The achieved EMI reduction is 10.488 dB when SSC turned on.
In the second chip work, a cyclic-Vernier time-to-digital converter (TDC) is proposed to achieve a high resolution TDC. Because of the cyclic structure, the dynamic range is wider and the consumed area is less. The loop filter and the DSM in the modulation controller in this work is one order higher than the first work to achieve better noise performance. The experimental chip is also designed for 1.5GHz SATA specification and is fabricated in a 0.18um CMOS process.
Abstract i

Table of Contents v

List of Figures ix

List of Tables xiii

Chapter 1
Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2

Chapter 2
Spread Spectrum Clock Generation Overview 5
2.1 Techniques to Reduce EMI 5
2.2 Spread Spectrum Fundamentals 8
2.2.1 Concepts 8
2.2.2 Spread Spectrum Modes and Amounts 10
2.2.3 Modulation Frequency 12
2.2.4 Modulation Profiles 13

Chapter 3
Overview & Design Flow for All Digital Phase-Locked Loops
17
3.1 Phase-Locked Loop Fundament 17
3.2 Linear Model of an ADPLL 19
3.2.1 Conversion Between the S- and Z-domain 19
3.2.2 Linear Model of the P2D 20
3.2.3 Linear Model of the DLF 21
3.2.4 Linear Model of the DCO 25
3.3 Design Parameters for type-II Second-Order ADPLLs 26
3.3.1 Design Parameters Calculation 27
3.3.2 A Design Example 28
3.4 Design Parameters for type-II Second-Order ADPLLs 31
3.4.1 Design Parameters Calculation 31
3.4.2 A Design Example 33
3.5 Design Flow of an ADPLL 35

Chapter 4
A 1.5GHz All-Digital Spread Spectrum Clock Generator for
SATA 39
4.1 Introduction 39
4.2 System Architecture and Circuits 41
4.2.1 Phase Frequency Detector for the Proportional
Path 42
4.2.2 Phase Frequency Detector for the Integral Path 44
4.2.2.1 Phase Selector 44
4.2.2.2 Phase Decision Circuit 46
4.2.2.3 Time Amplifier 47
4.2.2.4 5-bit Vernier TDC 48
4.2.3 Digital Controlled Oscillator 50
4.2.4 DCO Resolution Enhancement Circuit 53
4.2.5 Digital Delta-Sigma Modulator 54
4.2.6 Loop Filter 55
4.2.7 Dual-Modulus Divider 57
4.2.8 Programmable Down Counter 58
4.2.9 Delta-Sigma Modulator and Triangular Wave
Generator 59
4.3 System Simulation 62
4.3.1 Behavior Simulation 62
4.3.2 Mixed-Signal Co-Simulation 65
4.4 Experimental Results 66
4.5 Performance Comparison 70

Chapter 5
A 1.5GHz All-Digital Spread Spectrum Clock Generator
with a Cyclic-Vernier TDC for SATA 71
5.1 Introduction 71
5.2 System Architecture and Circuits 72
5.2.1 Phase Frequency Detector 73
5.2.2 Proposed Cyclic-Vernier TDC 73
5.2.3 Digital Controlled Oscillator 78
5.2.4 Digital Loop Filter 80
5.2.5 DSM for Modulation Controller 82
5.3 System Simulation 83
5.3.1 Behavior Simulation 83
5.3.2 Mixed-Signal Co-Simulation 86
5.4 Performance Summary 86

Chapter 6
Conclusions 89

Bibliography 91
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