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研究生:白尚謙
研究生(外文):Shang-Chien Pai
論文名稱:應用於睡眠電晶體之電流模型的靜態時序分析
論文名稱(外文):Sleep Transistor-Aware Modified Composite Current Source Model
指導教授:陳中平陳中平引用關係
指導教授(外文):Chung-Ping Chen
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:97
語文別:英文
論文頁數:46
中文關鍵詞:漏電功耗超大型積體電路睡眠電晶體電流源模型態時序分析
外文關鍵詞:VLSILeakage PowerSleep TransistorCurrent Source ModelsStatic Timing Analysis
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隨著製程技術不斷的進步,特徵尺寸不斷的縮小,目前45nm甚至是32nm的製程已經被大量且廣泛的使用。伴隨著製程的進步,漏電的情形也因為閘氧化層的厚度不斷變薄而日益嚴重。最新的研究指出,漏電功耗已經佔了整體功率的約 42%之多,成為了設計超大型積體電路不得不解決的問題。
睡眠電晶體(Sleep Transistor) 是一個被廣泛用來解決漏電的技術。他的原理是使用睡眠電晶體將不執行所需計算的邏輯閘關閉去改善漏電的問題。然而,由於睡眠電晶體兩端的電壓下降,導致傳統的電流源模型(Current Source Model)無法有效的準確靜態時序分析。
在本篇論文中,我們提出了一個改良的電流源模型(Modified Current Source Model)來同時模擬標準邏輯閘的輸出以及睡眠電晶體兩端的電壓下降的效應。實驗結果顯示我們跟HSPICE 模擬軟體的平均延遲誤差僅僅只有2%以下。
As the semiconductor technology advances, feature sizes continue to shrink. No-wadays 45nm technology and even 32nm technology have been largely employed in the design of modern Integrated Circuit Design. However with the advancement of shrink-ing feature sizes, comes the problem of leakage current. As the gate oxide thickness be-coming thinner with the advancing technology, this problem can no longer be ignored. The newest research results demonstrate that the leakage power accounts for 42% of total power and thus must be reduced for the design of VLSI circuits.
Sleep transistor is a vastly used technique for reducing leakage power. The theory behind it is to simply cut off the gates that are not in use to further reduce the leakage power. However the traditional Current Source Models for Static Timing Analysis have no consideration for the effect of the addition of a sleep transistor. This limits the design ability of circuits with sleep transistors and introduces uncertainties in the design.
In this thesis, we proposed a Modified Composite Current Source Model to not only model the output of standard gates but to model the effect of a non-stable ground. In addition this model demonstrates the ability of persevering the output waveform from stage to stage. There is no need of recalculating an input transition value after ever stage. Experimental results compared with HSPICE results show an average delay error of less than 2%.
1. Introduction 1
2. Background 5
2.1. Non-Linear Delay Models 5
2.2. Current Source Models 8
2.3. Other Current Source Models 9
2.4. Modified Composite Current Source Model 11
3. Characterization of MCCSM 13
3.1. Current Source Modeling 13
3.1.1. Singular Value Decomposition 17
3.1.2. Comparison of Model with Voltage Output 21
3.2. Parasitic Capacitance Modeling 22
4. Simulator Program 26
4.1. Nodal Analysis 27
4.2. Finite Difference 28
4.3. Variation with addition of Sleep Transistor 31
4.4. Simulation Flow 33
5. Experimental Results 35
5.1. Simulation of Individual Cell without Sleep Transistor 35
5.2. Propagation of Output Waveform through Different Stages 42
5.3. Simulation of Individual Cell with Sleep Transistor 43
6. Conclusion 45
References 46
[1]S. Borkar, "Design Challenges of Technology Scaling," IEEE Micro, pp. 23-29, July 1999.
[2]D. Duarte, V. Narayanan, M. J. Irwin, and M. Kandemir, "Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks," in VLSID, 2001, p. 248.
[3]G. E. Moore, "No exponential is forever: but "Forever" can be delay!," in ISSCC, 2003, pp. 20-23.
[4]J. Kao, S. Narendra, and A. Chandrakasan, "Subthreshold Leakage modeling and reduction techniques," in ICCAD, 2002, pp. 141-148.
[5]L. Wei et al., "Design and optimization of dual-threshold circuits for low-voltage low-power applications," in VLSI Systems, 1999, pp. 16-24.
[6]S. Sirichotiyakul et al., "Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing," in DAC, 1999, pp. 436-441.
[7]V. Khandelwal and A. Srivastava, "Leakage control through fine-grained placement and sizing of sleep transistors," in ICCAD, 2004, pp. 533-536.
[8]M. Anis, M. Mahmoud, M. Elmasry, and S. Areibi, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique,".
[9]J. Kao, S. Narendra, and A. Chandrakasan, "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns," in DAC, 1998, pp. 495-500.
[10]Y. Wang, Y. Liu, R. Luo, H. Yang, and H. Wang, "A Leakage Reduction Methodology for Distributed MTCMOS," IEEE JSSC, vol. 39, no. 5, pp. 818-826, May 2004.
[11]K. Chopra, C. Kashyap, H. Su, and D. Blaauw, "Current Source Driver Model Synthesis and Worst-case Alignment for Accurate Timing and Noise Analysis," in TAU, 2006.
[12]J. F. Croix and D. F. Wong, "Blade and razor: cell and interconnect delay analysis using current-based models," in DAC, 2003, pp. 386-389.
[13]V. Litovski and M. Zwolinski, VLSI Circuit Simulation and Optimization. London, UK: Chapman & Hall, 1997.
[14]L. T. Pillage, R. A. Rohrer, and C. Visweswariah, Electronic Circuit and System Simulation Methods.: McGraw-Hill, 1995.
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