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研究生:陳皇宇
研究生(外文):Huang-Yu Chen
論文名稱:考慮可靠度與可製造性之現代化超大型積體電路晶片繞線
論文名稱(外文):Modern VLSI Routing Considering Reliability and Manufacturability
指導教授:張耀文張耀文引用關係
指導教授(外文):Yao-Wen Chang
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:140
中文關鍵詞:超大型積體電路實體設計繞線繞線架構可靠度可製造性
外文關鍵詞:ManufacturabilityPhysical DesignReliabilityRoutingVLSI
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隨著超大型積體電路(VLSI)晶片技術進入奈米製程的時代,在奈米晶片實體設計中,繞線(routing)所造成的問題佔整體晶片設計效能的比例逐漸增加,而且面臨到許多問題,尤其是(1)設計複雜度、(2)可靠度(reliability)、及(3)可製造性(manufacturability)等三大問題急需去處理。因此,本篇論文提出了創新的繞線器來針對超大型積體電路晶片的設計複雜度解決晶片可靠度及可製造性問題。
早期的繞線問題是使用直接兩階段繞線方式(flat routing),也就是全域繞線(global routing)接續區域繞線(detailed routing)來處理繞線問題,但此解法受限在其對於處理大量資料時的延伸性;為了解決這問題,使用分而治之(divide and conquer)方式的階層繞線(hierarchical routing)被提出來降低問題的複雜度,但階層繞線的性能仍受限於其無法保留各切割區塊間的全域資訊。於是Λ型和V型多階層繞線器(multilevel routing)被發展出來解決以上架構所產生的問題。
跟據Λ型和V型這兩種多階層繞線架構,我們提出了兩種新的繞線架構:由細節到總體雙重操作繞線架構(two-pass bottom-up routing framework, TBF)及從總體到細節雙重操作繞線架構(two-pass top-down routing framework, TTF)來加快繞線速度、提升繞線完成度、及性能最佳化。除了此創新的繞線架構,我們也對雙導通孔保護(double-via insertion)可靠度問題以及化學機械研磨(chemical-mechanical polishing, CMP)和雙圖案微影技術(double-patterning technology, DPT)可製造性問題做了深入的研究。實驗結果證明,我們的創新架構比其他方法具有較好的彈性來處理以上的問題。跟之前發表在電子設計自動化重要會議發表的多階層繞線器相比,我們的方法在雙導通孔保護、化學機械研磨效應及雙圖案微影上,都有明顯的改善。
As nanometer technologies of very-large-scale integration (VLSI) advances, design complexity grows at a dramatic speed. Nowadays, a chip may contain several billion transistors and has over one million nets. In the nanometer era, routing has become a decisive factor for determining chip yield, since it presides over most of the layout geometries in the back-end design process. In this dissertation, new routing systems and algorithms are developed to tackle these challenges, for handling (1) increasing chip complexity, (2) reliability, and (3) manufacturability.

Traditional routing algorithms adopt a two-stage flat framework of global routing followed by detailed routing. However, the flat framework does not scale well as the design size increases. To cope with the scalability problem, a hierarchical framework is proposed, which uses the divide-and-conquer approach to handling smaller subproblems independently. Although the hierarchical approach can scale to larger designs, it has a drawback of lacking interactions among routing subregions and thus limits the solution quality. To remedy the deficiencies, researchers have proposed various multilevel frameworks to handle large-scale routing problems. The λ-shaped multilevel routing framework consists of bottom-up coarsening followed by top-down uncoarsening, while the V-shaped one consists of top-down uncoarsening followed by bottom-up coarsening. The multilevel frameworks demonstrate the superior capability of handling large-scale routing problems and the versatility of tackling modern nanometer electrical effects.

Based on these two multilevel frameworks, we develop new routing frameworks, namely TBF (Two-pass, Bottom-up routing Framework) and TTF (Two-pass, Top-down routing Framework), to accelerate the routing speed, enhance the routability, and improve the performance. Moreover, we propose new routing methodologies considering design for reliability and manufacturability issues.

To enhance the reliability through redundant-via insertion, we present a new full-chip routing system considering double-via insertion for yield enhancement. To fully consider double vias, the router applies the TBF routability-driven routing framework and features a new redundant-via aware detailed routing algorithm to improve the via count, the number of dead vias, and double-via insertion rates.

To increase manufacturability and reduce the post-CMP (chemical-mechanical polishing) topography variation, we present a new full-chip routing system considering wire density for reticle planarization enhancement. To fully consider wire distribution, the router applies the TTF planarity-driven routing framework which employs a density critical area analysis (DCAA) based on Voronoi diagrams and incorporates an intermediate stage of density-driven layer/track assignment based on incremental Delaunay triangulation.

To cope with the manufacturing problem considering the layout decomposition in DPT (double-patterning technology), we present a rule-based DPT-aware routing system to reduce conflicts and stitches for grid-based designs. Specifically, our router can guarantee 100% splitting without DPT conflicts, considering vertical-horizontal patterns. The router embeds a fast layout decomposition (FLD) algorithm as a cost evaluator which consists of two major stages: (1) alternating-coloring conflict removal, and (2) two-phase stitch minimization. In addition, the approaches to improve the scalability of the proposed algorithms are also leveraged for large-scale designs.
Acknowledgements ii
Abstract (Chinese) iv
Abstract xii
List of Tables xvii
List of Figures xviii
Chapter 1. INTRODUCTION 1
1.1 Physical Design Flow 1
1.2 Routing Requirements for the Nanometer Era 3
1.2.1 Reliability Issue 3
1.2.2 Manufacturability Issue 5
1.3 Overview of the Dissertation 12
1.3.1 Routing Model and Routing Framework 12
1.3.2 Full-Chip Routing Considering Double-Via Insertion 13
1.3.3 Full-Chip Routing Considering CMP Variation Control 13
1.3.4 Full-Chip Routing Considering Double-Patterning Technology 14
1.4 Organization of the Dissertation 14
Chapter 2. ROUTING MODEL AND ROUTING FRAMEWORK 15
2.1 Problem Definition 15
2.2 Routing Model 16
2.2.1 Global Routing Model 17
2.2.2 Detailed Routing Model 19
2.2.3 Routing Constraints 20
2.3 Traditional Routing 22
2.3.1 Flat Routing Framework 22
2.3.2 Hierarchical Routing Framework 31
2.4 Modern Routing Framework 33
2.4.1 Previous Multilevel Routing Framework 33
2.4.2 Two-pass Bottom-up Routing Framework 40
2.4.3 Two-pass Top-down Routing Framework 42
2.4.4 Summary of Modern Routing Framework 44
Chapter 3. FULL-CHIP ROUTING CONSIDERING
DOUBLE-VIA INSERTION 46
3.1 Redundant-Via Insertion 46
3.2 Preliminaries 48
3.2.1 Double-Via Insertion 48
3.2.2 Gridless Detailed Routing Model 50
3.3 Redundant-Via Aware Routing 52
3.3.1 Congestion-Driven Prerouting Stage 52
3.3.2 Via-Minimization Global Routing Stage 54
3.3.3 Redundant-Via Aware Detailed Routing Stage 55
3.4 Experimental Results 57
Chapter 4. FULL-CHIP ROUTING CONSIDERING
CMP VARIATION CONTROL 62
4.1 Chemical-Mechanical Polishing 62
4.2 Density-Driven Routing 68
4.2.1 Density Critical Area Analysis 68
4.2.2 Planarization-Aware Global Routing 72
4.2.3 Density-Driven Layer/Track Assignment 73
4.2.4 Segment-to-Segment Detailed Routing 85
4.3 Experimental Results 86
Chapter 5. FULL-CHIP ROUTING CONSIDERING
DOUBLE-PATTERNING TECHNOLOGY 95
5.1 Double-Patterning Technology 95
5.2 Preliminaries 100
5.3 Zero-Conflict DPT-Aware Routing 104
5.3.1 Alternating-Coloring Conflict Removal 105
5.3.2 Two-Phase Stitch Minimization 108
5.4 Experimental Results 115
Chapter 6. CONCLUDING REMARKS AND FUTURE WORK 120
6.1 Routing Model and Routing Framework 120
6.2 Full-Chip Routing Considering Double-Via Insertion 121
6.3 Full-Chip Routing Considering CMP Variation Control 122
6.4 Full-Chip Routing Considering Double-Patterning Technology 122
6.5 Future Work 123
Bibliography 126
Vita 138
Publication List 139
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