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研究生:林家華
研究生(外文):Chia-Hua Lin
論文名稱:支援OpenCV函式庫視訊信號處理器之架構設計與實作
論文名稱(外文):Design and Implementation of Vision Signal Processor with OpenCV Library Support
指導教授:陳良基陳良基引用關係
指導教授(外文):Liang-Gee Cheng
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:英文
論文頁數:85
中文關鍵詞:視訊信號處理器臉部偵測
外文關鍵詞:visionprocessoropencvface detection
相關次數:
  • 被引用被引用:0
  • 點閱點閱:733
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  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:1
本篇論文中提出一個高效率的視覺信號處理器架構設計並支援OpenCV 函式庫,
此晶片運算輸出為64GOPS,功率消耗86.5mW,在UMC 90nm Logic&Mixed Mode 1P9M
Low-K 製程下,面積為2.75mm x 2.75mm。
近年來,視訊分析技術在視訊應用上面扮演著越來越重要的角色,例如監視系
統、健康醫療照護、智慧型車輛駕駛系統等等,我們相信智慧型視訊分析技術會
是未來的發展趨勢。
Intel OpenCV 函式庫近期在相關研究領域上相當受歡迎,並創造出許多成功的
應用。本篇論文所提出的硬體架構可以提供一對一的函式轉換,讓原本在電腦端
執行的函式直接轉移到嵌入式系統中,這樣的硬體不但可以節省演算法的開發時
間,更可以加速產品上市的時間。
型態學上的運算是電腦視覺中最常被使用的函式,通常是許多影像辨識的前處理
過程。實驗結果顯示我們所提出的架構可以提供高運算輸出及低功率消耗,對於
一張1024 x 768 的灰階影像,運算速度可達每秒兩百張影像,同時,相較於目前
可見的其他影像處理器,此架構僅需相當小的面積。
除了型態學的運算之外,快速的物件偵測是電腦視覺領域上的另一個挑戰。Viola
及Jones 提出了一個快速偵測物件的演算法,被OpenCV 採用,我們也將此演
算法針對我們的硬體作最佳化的設計,我們採用CMU+MIT 的臉部偵測的標準
測試圖樣來測試我們修改過後的演算法, 119 張影像中含有513 張臉,實驗結
果顯示我們的偵測率為87.3%,運算速度在320x240 的影像大小下可達每秒10
張。
An efficient architecture design of vision signal processor with OpenCV library support
is presented in this thesis. It is a 64GOPS, 86.5mW vision processor which is implemented
on a 2.75mm£2.75mm die in a UMC 90nm Logic&Mixed-Mode 1P9M Low-K
Process.
In the resent decades, video analysis technology plays more and more important role
in many vision applications, such as surveillance system, healthcare, intelligent vehicle
system and so on. It is believed that intelligent video analysis technology will must be
the trends of development.
Nowadays, Intel OpenCV library is popular in the research domain and creates lot’s
of successful applications. Our hardware can provide one to one function mapping from
PC OpenCV library to embedded system. With this hardware, the implementation time
can be saved and speed up the product become available in the market.
One of the most frequently used operations in image recognitions morphological
processing, which is often adopted for pre-processing of various applications based on
image recognition. Experimental result shows our proposed architecture performs high
computation throughput and low power consumption. It can process 1024£768 8-bit
gray level image with more than 200 frames per second and the area is quite small
compared to state-of-the-arts.
Robust and rapid object detection is the other challenge in the field of computer
vision. A object detection algorithm proposed by Viola and Joses is implemented in
our design. We optimize the algorithm to our hardware with low performance drop.
Detection rate for CMU+MIT test database which consists of 119 images with 513
labeled frontal faces is 87.3%. The processing speed is 10 frames per second with
320£240 8-bit gray level image
1 Introduction 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Current Development of Vision Processor . . . . . . . . . . . . . . . . 2
1.3 Design Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Overview of OpenCV Library 7
2.1 Introduction to OpenCV . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 OpenCV Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Application (I) —Object detection . . . . . . . . . . . . . . . . . . . 10
2.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2 Adaboost Algorithm . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.3 Integral Image . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.4 Cascade Classifier . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Application (II)—Image Signal Processing . . . . . . . . . . . . . . . 18
2.5 Application (III)—Fall Detection . . . . . . . . . . . . . . . . . . . . 23
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 Design of Vision Signal Processor 27
3.1 Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Design Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 Benchmark Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.1 Morphological Operation . . . . . . . . . . . . . . . . . . . . . 30
3.4.2 Haar-feature Object Detection . . . . . . . . . . . . . . . . . . 31
3.4.3 Architecture Design Strategy . . . . . . . . . . . . . . . . . . . 32
3.4.4 Analysis of Tile-based Processing . . . . . . . . . . . . . . . . 36
3.5 Design Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5.1 Tile-based image stream processing . . . . . . . . . . . . . . . 38
3.5.2 Integral intelligent image processing unit . . . . . . . . . . . . 39
3.5.3 Parallel mask conditional operation . . . . . . . . . . . . . . . 40
3.6 Architecture Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.6.1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . 43
3.6.2 Tile Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.6.3 SIMD Image Processor . . . . . . . . . . . . . . . . . . . . . . 47
3.6.4 Instruction Set Architecture . . . . . . . . . . . . . . . . . . . 52
3.7 Optimization of Haar-Feature Object Detection Algorithm for Our Architecture
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4 Chip Implementation 63
4.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2 FPGA Verification and Demonstration . . . . . . . . . . . . . . . . . . 65
4.2.1 FPGA Verification . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.2 FPGA Demonstration . . . . . . . . . . . . . . . . . . . . . . 66
4.3 Chip Specification and Layout . . . . . . . . . . . . . . . . . . . . . . 67
4.4 Experimental Result and Comparison . . . . . . . . . . . . . . . . . . 67
5 Conclusion 79

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