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研究生:陳勝堯
研究生(外文):Sheng-Yao Chen
論文名稱:最大有效位元優先的非同步加比選單元
論文名稱(外文):An MSB-First Asynchronous Add-Compare-Select Unit
指導教授:盧奕璋
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:76
中文關鍵詞:非同步電路設計單軌全緩衝器電路最大有效位元優先比較進位儲存加法加比選單元
外文關鍵詞:Asynchronous designSingle-Track Full-Buffer circuitsMSB-First comparisonCarry-save additionAdd-Compare-Select unit
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隨著科技的進步,晶片的面積有逐漸擴大的趨勢,再加上晶片的時脈速度不斷的提高,都使得同步電路設計的困難度越來越高。當使用的製程越先進,時脈分佈和降低時脈時滯的議題也顯得更加重要。除此之外,也許晶片的某部分電路已經完成了運算,但它仍然必須等待晶片中最慢的電路完成才能繼續下一筆的運算。為了解決這些問題,有研究提出了非同步電路設計。
在本論文中,我們提出了一個用於維特比解碼器中的加比選單元,此單元由非同步單軌電路設計而成。由於維特比解碼器的效能瓶頸在於加比選單元,提高加比選單元的效能也能增進維特比解碼器的效能。藉由採用進位儲存加法及最大有效位元優先的比較,我們可以充份的利用非同步電路設計的優點,也就是電路運算的速度會隨著輸入資料的不同而有所改變。我們也分析了我們所提出的電路的平均效能。假設資料的位元樣式發生的機率皆是相等的話,可以證明我們的運算效能幾乎和輸入的字組長度無關。和其它不同的設計方式相比,實驗結果顯示我們所提出的電路有較佳的效能。以常數電場縮放來做計算的話,在效能上與一般靜態電路相比,可達到88.6%的提昇。甚至與目前最快的自我重設式電路相比,在效能上也有18.5%的提昇。在硬體實作上,利用TSMC 0.18μm 1P8M的製程來實現非同步加比選單元及其測試電路。實現的晶片面積為1.278mm x 1.018mm。
As the advance in the technology, chips have become larger and larger, and it becomes more difficult for synchronous design, particularly as clocks get faster. The problems of clock distribution and clock skew minimization are becoming increasingly significant as the technology scales. Besides, the tasks performed on parts of a chip that are close together finish well before a cycle but can’t move on until the next clock cycle. To cope with this problem, some studies have proposed asynchronous design styles.
In this thesis, we present a new Add-Compare-Select unit for Viterbi Decoders implemented with a 1-of-N asynchronous single track template. The Viterbi decoder is mainly restricted by the performance bottleneck – the ACS unit. If we can improve the performance of ACS unit, the performance of Viterbi decoder can be sped up, too. By adopting carry-save addition and most-significant-bit-first (MSB-First) comparison, we can fully utilize the advantages of asynchronous circuit so that the computation speed can vary with different input data patterns. We also analyze the expected performance given that every data pattern has the same probability of occurrence. Under that assumption, we can prove that the word length would not affect the performance of our design. A comparison between different circuit styles is also provided, which shows the performance of our design is potentially better than other designs. By constant field scaling, it can be seen that our design has 88.6% improvement in throughput when comparing with static CMOS design. It even has 18.5% improvement in throughput when comparing with fastest state-of-art self-resetting CMOS circuit style. In hardware implementation, our ACS unit and test circuit design are implemented in TSMC 0.18-μm CMOS process. The die size is 1.278mm x 1.018mm giving a total area of 1.30 mm2.
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Previous Works of Add-Compare-Select Unit 4
1.3 Design Flow and Organization 7
Chapter 2 Background 11
2.1 Asynchronous Channels 11
2.2 Asynchronous Templates 14
Chapter 3 Single-Track Full-Buffer Circuits 19
3.1 Add-Compare-Select Unit Structure 19
3.2 Output Circuitry 20
3.3 Adders 21
3.4 Code Converter and Maximum Selection Stages 23
3.4.1 Code Converter 23
3.4.2 Maximum Selection Stage 25
3.4.3 Maximum Selection First Stage 28
3.4.4 Maximum Selection Last Stage 29
3.5 1-of-2 Encoded Non-conditional Merge and 1-of-2 Encoded Fork4 30
3.6 1-of-2 Encoded Multiplexer and 1-of-3 Encoded Multiplexer 32
3.7 Request Signal Converter and 1-of-2 Encoded Bucket 34
3.8 1-of-2 Encoded Buffer 35
3.9 Initialization Circuit 35
3.10 1-of-2 Encoded and 1-of-3 Encoded Test Circuits 36
3.10.1 Single-Rail to 1-of-2 Encoded Single-Track Converter 38
3.10.2 Single-Rail to 1-of-3 Encoded Single-Track Converter 39
3.10.3 1-of-2 Encoded Fork and 1-of-3 Encoded Fork 39
3.10.4 1-of-2 Encoded and 1-of-3 Encoded Conditional Merge 41
3.10.5 1-of-3 Encoded Buffer 43
3.10.6 Bit Generator 44
3.11 Sampler 45
3.11.1 1-of-2 Encoded Split and 1-of-3 Encoded Split 46
3.11.2 1-of-3 Encoded Bucket 48
3.11.3 1-of-2 Encoded Single-Track to Single-Rail Converter 49
3.11.4 1-of-3 Encoded Single-Track to Single-Rail Converter 50
Chapter 4 Simulation Results and Comparison 53
4.1 Simulation Results 53
4.2 Performance Analysis 61
4.3 Comparison 64
Chapter 5 Chip Implementation and Measurement 67
5.1 Introduction and I/O Consideration 67
5.2 The Chip Layout 68
5.3 Measurement 70
Chapter 6 Conclusion 71
Reference 73
[1] C. Tristram, “It’s time for clockless chips,” Technology Review, pp. 36-41, Oct. 2001.
[2] S. Hauck, “Asynchronous design methodologies: An overview,” Proc. of IEEE, vol. 83, no. 1, pp. 69–93, Jan. 1995.
[3] J. Sparso and S. Furber, Principles of Asynchronous Circuit Design - A Systems Perspective, Springer, Inc, 2001, pp. 3-8.
[4] G. D. Fomey, Jr., “The Viterbi algorithm,” Proc. of IEEE, vol. 61, no. 3, pp. 268-278, Mar. 1973.
[5] S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, PEARSON/ Prentice Hall, second edition,2004.
[6] A. Eshraghi et al., “Asynchronous implementation of the Add Compare Select Processor for Communication Systems,” in Proceedings of IEEE Int’l Symposium on Circuit and Systems, vol. 3, pp. 253-256, 1994.
[7] K. K. Parhi, “An improved pipelined MSB-first add-compare select unit structure for Viterbi decoders,” IEEE Transactions on Circuits and Systems I: Regular Papers 51(3), pp. 504-511, 2004.
[8] M. K. Akbari et al., “Area efficient, low power and robust design for Add-Compare-Select units,” in Proceedings of Euromirco Symposium on Digital System Design, pp. 611-614, 2004.
[9] J. Gunok et al., “Hig-speed Add-Compare-Select units using locally self-resetting CMOS,” in Proceedings of IEEE Int’l Symposium on Circuit and Systems, vol. 1, pp. 889-892, 2002.
[10] M. Ferretti, R. O. Ozdag and P. A. Beerel, “High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells,” in Proceedings of 10th International Symposium on Asynchronous Circuits and Systems, 2004., pp. 95-105, 2004.
[11] W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge 1998.
[12] C. Myers, Asynchronous Circuit Design, John Wiley and Sons, July 2001.
[13] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, New York: Wiley, 1999.
[14] A. M. Lines, “Pipelined asynchronous circuit,” Master Thesis, California Institute of Technology, June 1998.
[15] I. Sutherland and S. Fairbanks, “GasP: a minimal FIFO control,” in Proceedings of ASYNC, pp. 46-53, 2001.
[16] M. Ferretti and P.A. Beerel, “Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding”, in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, 2002., pp. 1008-1015, 2002.
[17] M. Ferretti and P. A. Beerel, “High performance asynchronous design using single-track full-buffer standard cells,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1444-1454, June 2006.
[18] M. Ferretti, “Single-track asynchronous pipeline template,” Ph.D. dissertation, Univ. of Southern California, Los Angeles, Aug. 2004.
[19] G. Fettweis and H. Meyr, “High-rate Viterbi processor: a systolic array solution,” IEEE J. Selected Areas in Communications, vol. 8, no. 8, pp. 1520-1534, Aug. 1990.
[20] G. Fettweis and H. Meyr, “High-speed parallel Viterbi decoding: algorithm and VLSI-architecture,” Communications Magazine, IEEE 29(5), pp. 46-55, 1991.
[21] N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Reading, MA: Addison-Wesley, 2005.
[22] P. Golani, G.. D. Dimou, M. Prakash and P. A. Beerel, “Design of a High-Speed Asynchronous Turbo Decoder,” in 13th IEEE International Symposium on Asynchronous Circuits and Systems, 2007., pp. 49-59, 2007.
[23] P. A. Riocreux, L. E. M. Brackenbury, M. Cumpstey and S. B. Furber, “A low-power self-timed Viterbi decoder,” in Seventh International Symposium on Asynchronous Circuits and Systems, 2001., pp. 15-24, 2001.
[24] M. Kawokgy and C. A. T. Salama, “Low-power asynchronous Viterbi decoder for wireless applications,” in Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004., pp. 286-289, 2004.
[25] C. K. Tang, C. Y. Lin, Y. C. Lu, “An asynchronous circuit design with fast forwarding technique at advanced technology node,” in 9th International Symposium on Quality Electronic Design, 2008., pp. 769-773, 2008.
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