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研究生:張家銘
研究生(外文):Chia-Ming Chang
論文名稱:適用於衛星導航信號擷取之新式相關器演算法與VLSI設計
論文名稱(外文):Novel Algorithm and VLSI Design of Correlation Architecture for GNSS Signal Acquisition
指導教授:曹恆偉曹恆偉引用關係
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:96
中文關鍵詞:全球衛星定位系統信號擷取相關器子運算平行相位搜尋
外文關鍵詞:GPSacquisitioncorrelatorsubexpressionparallel phase search
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相關器(Correlation Architecture)為一種廣泛使用於各種通訊系統接收端上的裝置,尤其對於展頻系統信號擷取(Signal Acquisition)的模式中,相關器更是扮演著不可或缺的角色。而隨著全球導航衛星系統(Global Navigation Satellite Systems)的成熟發展,包括像是美國的GPS系統,歐盟的Galileo系統,乃至於俄國GLONASS系統,甚至日本,中國等國家都預計於未來數十年內發展出一套可提供多種服務的商用衛星裝置。因此,為了提供商用更快速的導航能力,信號擷取的初始定位時間(Time To First Fix)便成為各種接收裝置效能好壞的重要指標。而在決定信號擷取的初始定位時間中,相關器的設計佔有極為重要的影響能力。
由信號擷取中相位搜尋的不同方式,以及相關器的種類,可歸納出現行三種常用的接收端信號擷取架構;分別為循序輸入相關器加上平行相位搜尋,匹配濾波器加上序列相位搜尋,及快速傅利葉轉換等方式。而其中,匹配濾波器加上平行相位搜尋的方式,雖然效能卓越,但是因為架構太複雜且成本太高,所以一般設計很少有人使用這種方法。本篇論文的目標就是在衛星導航的系統下,提出一套有效率的演算法設計流程,透過子運算簡化(subexpression elimination)的方式,設計出有效率的硬體結構,其優點為縮小晶片面積、提高硬體使用率、縮短初始定位時間和低功率的消耗等。另外,若運用在軟體接收機的應用上,演算法的彈性設計更可大幅縮減所要計算的加乘次數。
在硬體實作上,透過標準單元的設計流程,利用0.18um的製程來實踐所提出的相關器架構。所實現的架構可支援同時搜索32種GPS L1 C/A碼(Coarse/Acquisition Code)信號,晶片面積約為1.86mm × 1.86mm。
Correlation architectures are widely used in various communication systems’ receiver, especially for the spread spectrum system, and they play an indispensable role in signal acquisition. With the mature development of GNSS (Global Navigation Satellite Systems), such as the GPS of U.S., the Galileo system of European Union, as well as the GLONASS of Russian, and even Japan, China are developing their own commercial satellites system to offer wide range of services. Therefore, in order to provide faster commercial navigation ability, the TTFF (Time To First Fix) of signal acquisition becomes one important indicator to gauge the performance of various kinds of receivers. Among these receivers, the design of correlator has the most important influence on TTFF.

From different code phase searching methods of signal acquisition, and different types of correlators, we can conclude three common signal acquisition receiver architectures: sequential-input correlator with parallel code phases search, matched-filter with serial code phase search and fast Fourier transform method. Among these methods, the hardware complexity and the cost are too high for matched-filter with parallel code phases search although its TTFF is shortest. Therefore, only few people adopt this method in practical design. For this reason, this thesis proposed one efficient algorithm design flow for navigation satellites systems. By using subexpression elimination method, we designed an efficient hardware architecture which has advantages of area reduction of die size, enhancement of hardware utilization, reduction of TTFF, and low power consumption, etc. In addition, for software receiver application, the flexible design of the algorithm can tremendously reduce the required number of addition and multiplication.

In hardware implementation, the proposed correlator architecture is implemented in 0.18 um CMOS process. The proposed design can provide searching 32 GPS L1 C/A code signals simultaneously and the implemented die size is about 1.86mm × 1.86mm.
致謝 …………………………………………………………..….…...…………..… VII
中文摘要 …………………………………………………………..……..………..… IX
Abstract …………………………………………………………………...….……… XI
Table of Contents ………………………………..……………………………….... XIII
List of Figures …………………………………………………………………..… XVII
List of Tables ………………………………………………………………………. XXI

Chapter 1: Introduction ……………………………………………………………… 1
1.1 Overview of Global Navigation Satellites System …………………… 1
1.2 Research Topic, Motivation and Main Contributions ………………… 4
1.3 Thesis Organization …………………………………………………... 6

Chapter 2: Global Navigation Satellites System ………………………………..…... 9
2.1 Fundamentals of Satellite Navigation ………………………………… 9
2.2 Satellite Signal Characteristics ……………………………………… 11
2.3.1 Modulation Types …………………………………………… 11
2.3.2 Frequency Plan and Signal Design ………………………….. 13
2.3 Receiver Architectures ………………………………………………. 16
2.3.1 Antenna Consideration ……………………………………… 16
2.3.2 Amplifier Consideration …………………………………….. 17
2.3.3 ADC Consideration ………………………………………….. 17
2.3.4 Acquisition and Tracking Consideration ……………………. 18
2.4 Summary …………………………………………………………….. 19

Chapter 3: Acquisition Algorithms ………………………………………………… 23
3.1 State of the Art ………………………………………………………. 23
3.1.1 Sequential Input Correlator with Parallel Code Phase Search . 26
3.1.2 Matched-filter with Serial Code Phase Search ……………… 27
3.1.3 FFT …………………………………………………………... 29
3.1.4 Comparison of Conventional Correlation Architectures ……. 31
3.2 The Proposed Algorithm …………………………………………….. 34
3.2.1 Subexpression Elimination Concept ………………………… 35
3.2.2 Algorithm Flowchart ………………………………………… 37
3.2.3 Algorithm Applications and Simulation Results ……………. 44
3.3 Permutation Problems of the Proposed Algorithm ………………….. 49
3.3.1 Effect of Random Permutation of 32 PRN Codes …………... 49
3.3.2 Solution ……………………………………………………… 51
3.3.3 Estimation Formula for the Proposed Algorithm ……………. 56
3.4 Comparison of Different Algorithms ………………………………... 59
3.5 Summary …………………………………………………………….. 61

Chapter 4: Architecture Design for Correlation and Acquisition ………………... 65
4.1 The Proposed Correlation Scheme ………………………………….. 65
4.1.1 Postfiltering Technique ……………………………………… 65
4.1.2 Architecture Design for Correlation ………………………… 70
4.2 The Proposed Acquisition Scheme ………………………………….. 72
4.2.1 Architecture Design for Acquisition ………………………… 72
4.2.2 Simulation Results …………………………………………... 76
4.3 Fix-point Analysis …………………………………………………… 79
4.4 Summary …………………………………………………………….. 82

Chapter 5: Chip Implementation …………………………………………………... 83
5.1 Cell-based Design Flow ……………………………………………... 83
5.2 RTL Coding and Simulation ………………………………………… 84
5.3 Synthesis, DFT, ATPG and Gate-level Simulation ………………….. 86
5.4 Place and Route, DRC & LVS, and Post-layout Gate-level Simulation …………………………………………………………… 88
5.5 Comparison ………………………………………………………….. 91
5.6 Summary …………………………………………………………….. 92

Chapter 6: Conclusions ……………………………………………………………... 93
6.1 Conclusions and Main Contributions ……………………………….. 93
6.2 Future Works ………………………………………………………… 95

Abbreviations ………………………………………………………………………….. i
References …………………………………………………………………….……… iii
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