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研究生:陳俊諭
研究生(外文):Chun-Yu Chen
論文名稱:適用於未來無線廣域網路的高吞吐量可重組化迴旋渦輪解碼器設計
論文名稱(外文):High-Throughput Reconfigurable Convolutional Turbo Decoder Design for Future Wireless WAN
指導教授:吳安宇吳安宇引用關係
指導教授(外文):An-Yeu Wu
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:67
中文關鍵詞:迴旋渦輪碼高吞吐量可重組化平行化
外文關鍵詞:Convolutional Turbo Codehigh-throughputreconfigurableparallel
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由於無線設備使用者對於多媒體影音傳輸的需求與日俱增,對於未來的無線廣域網路,如3GPP-LTE與WiMAX系統,都已訂製符合高傳輸速率(100Mbps)的需求。近年來為了增加傳輸的可靠度,這些無線廣域網路系統開始納入更先進的通道碼技術。其中,1993年由Berrou等人所發現的單二元迴旋渦輪碼,已經被證實具有接近向農邊界的解碼效能。接著在1999年,在一時間編解碼兩筆位元的雙二元迴旋渦輪碼被提出,並被認為具有更佳的編碼增益。此兩種形式的渦輪碼已分別為3GPP-LTE系統與WiMAX系統所採用。
此篇論文的主要目標即是設計一套適用於未來無線廣域網路的高吞吐量且可重組化的迴旋渦輪解碼器. 此設計具備下列特色: 1) 針對迴旋渦輪解碼器的兩個主要組成單元:最大事後機率解碼器與交錯器提出新架構來提升吞吐量。2) 利用單二元迴旋渦輪碼與雙二元迴旋渦輪碼演算法上的運算相似性,設計可重組化的最大事後機率解碼器與交錯器以支援此兩種不同形式的迴旋渦輪碼。3) 以3GPP-LTE與WiMAX系統的迴旋渦輪碼規格為設計標的。合成結果證實在少於10%的硬體多於成本下,可使最大事後機率解碼器達到支援兩種迴旋渦輪碼演算法的目標。交錯器則可使用64.2%的硬體成本產生3GPP-LTE與WiMAX系統所要的交錯位置。
最後,將所提出的最大事後機率解碼器與交錯器整合至迴旋渦輪解碼器中。在晶片實現上,所提出的迴旋渦輪解碼器使用TSMC 0.13 μm 1P8M的先進製程來實現,晶片面積為7.02 mm2,且最高可操作的頻率為147 MHz。此解碼器可以支援3GPP-LTE系統與WiMAX系統共34種不同的操作模式,並且可達到260.2 Mbps的最高資料傳輸率,符合未來無線廣域網路的傳輸需求。
With the rapid growth of multimedia service demand, the data-rate requirement will be higher than 100 Mbps for future wireless WAN, such as 3GPP-LTE and WiMAX systems. In recent years, these wireless WAN systems have adopted advanced channel coding schemes in order to increase transmission reliability. Among them, the single-binary convolutional turbo code (SB-CTC) introduced by Berrou et al. in 1993 had been proved to have decoding performance close to the Shannon limit. Then, in 1999, the double-binary CTC (DB-CTC) was proposed to encode/decode two bits per time and yield to better coding gain compared with the SB-CTC. The SB- and DB-CTC schemes have been adopted in 3GPP-LTE and WiMAX systems, respectively.
The goal of this thesis is to design a high-throughput reconfigurable CTC decoder that can be used in future wireless WAN systems. The features are 1) propose new architecture for the MAP decoder and interleaver, the two main components of the CTC decoder, to achieve high-throughput requirement, 2) design the reconfigurable MAP decoder and interleaver based on the computational similarity between SB-CTC and DB-CTC decoding algorithms, and 3) target the CTC specification of 3GPP-LTE and WiMAX systems. The synthesis results show that the hardware overhead for the MAP decoder to support both CTC decoding algorithms is less than 10%. And only 64.2% hardware resource is required to generate the interleaved address of both 3GPP-LTE and WiMAX systems.
Finally, the proposed MAP decoder and interleaver are embedded into a CTC decoder. By using TSMC 0.13 μm 1P8M CMOS process, the proposed CTC decoder is implemented in a chip at 147 MHz maximum operating frequency with core size of 7.02 mm2. The implemented decoder can support 34-mode CTC decoding for both 3GPP-LTE and WiMAX systems. The maximum throughput rate can achieve 260.2 Mbps which satisfies the data-rate requirement of the future wireless WAN systems.
Contents
Abstract V
Contents VII
List of Figures IX
List of Tables XI
Chapter 1 Introduction 1
1.1 Introduction of Convolutional Turbo Codes 1
1.2 Motivation & Goal 2
1.3 Thesis Organization 5
Chapter 2 Review of Convolutional Turbo Codes 7
2.1 Typical CTC Encoder/Decoder Structure 7
2.2 MAP Decoding Algorithm 9
2.3 Timing Chart of MAP Decoding 14
Chapter 3 High-Throughput Dual-Mode MAP Decoder Design 17
3.1 Warm-up Free Parallel-Window MAP Decoding 17
3.2 Key Components Design for Dual-Mode MAP Decoder 22
Chapter 4 Parallel Dual-Standard Interleaver Design 37
4.1 Introduction of Interleaver 37
4.2 Parallel Interleaver Design 40
4.3 Dual-Standard Address Generator Design 45
4.4 Experimental Results 48
Chapter 5 VLSI Design of High-Throughput 34-Mode CTC Decoder 53
5.1 Throughput Analysis 54
5.2 Determination of Wordlength 55
5.3 VLSI Architecture of Proposed 34-Mode CTC Decoder 57
5.4 Chip Implementation 58
Chapter 6 Conclusions 63
Reference 65
Reference
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