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研究生:錢群元
研究生(外文):Chun-Yuan Chien
論文名稱:使用0.5V多重臨界電壓技術單相位時序(TSPC)動態邏輯電路於乘法器設計
論文名稱(外文):0.5V MTCMOS Technique TSPC Dynamic Logic Circuit using for a Multiplier Design
指導教授:郭正邦郭正邦引用關係
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:49
中文關鍵詞:乘法器全加器管線化單相位時序動態電路
外文關鍵詞:TSPCpipelineBP-DTMOSMultiplierFull Adder
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本篇論文研究主要是探討動態電路使用BP-DTMOS/MTCMOS技術於全加器以及乘法器在功率消耗與速度的最佳化。 首先敘述CMOS技術的發展趨勢以及超大型積體電路低電壓操作的需求,並且介紹BP-DTMOS技術。第二章描述低電壓下使用BP-DTMOS/MTCMOS具有閂鎖(TSPC)以及沒有閂鎖(NORA)動態電路的操作原理,除此之外使用BP-DTMOS/MTCMOS技術的全加器電路也被敘述。第三章敘述一個動態邏輯電路以及BP-DTMOS/MTCMOS技術的(pipeline)TSPC乘法器電路。第四章則是結論與未來研究方向。
This thesis reports BP-DTMOS/MTCMOS technology used in the full adder and the multiplier for optimization of power consumption and speed performance. First, evolution trends of CMOS technique and the low voltage operation requirement of VLSI circuit are described. Then BP-DTMOS technology is introduced. Chapter 2 describes the principle of low voltage dynamic logic circuit with and without latch using BP-DTMOS/MTCMOS technology. In addition, a full adder circuit using BP-DTMOS/MTCMOS technology is described. In Chapter 3, a dynamic logic circuit and DTMOS/MTCMOS technology pipelined multiplier using the 0.5V true single-phase clock (TSPC) is described. Chapter 4 is the conclusion and future work
of this research.
口試委員會審定書...........................................i
致謝.....................................................iii
中文摘要..................................................iv
ABSTRACT...................................................v
目錄......................................................vi
圖目錄....................................................ix
Chapter 1 導論............................................1
1.1低操作電壓的趨勢........................................1
1.2 CMOS 電路的消耗功率...................................2
1.3 低電壓單相位時序(TSPC)電路...........................4
1.4 BP-DTMOS ( Bulk PMOS dynamic threshold)技術............4
1.4.1 BP-DTMOS元件介紹....................................5
Chapter 2 使用 BP-DTMOS/MTCMOS 技術用於單相位時序全加器電路
(TSPC Full Adder Circuit)........................7
2.1 BP-DTMOS/MTCMOS結構使用於FA P-Unit DL..................8
2.2 動態電路技術..........................................11
2.2.1 動態電路簡介........................................11
2.2.2 TSPC電路基本架構....................................11
2.2.3 操作原理............................................12
2.2.4 動態電路的電荷注入問題 (Charge-injection)...........14
2.2.5 其他常見動態的電路設計考量..........................17
2.3 NORA(No Latch)全加器電路使BP-DTMOS/MTCMOS結構分析.....20
2.3.1 NORA全加器電路......................................20
2.4 單相位時序全加器電路使用BP-DTMOS/MTCMOS結構分析.......27
2.4.1 單相位時序全加器電路................................27
2.4.2 TSPC全加器對於BP-DTMOS/MTCMOS、HVT、LVT在相同CLK操作速
度下功率消耗比較結果................................37
2.4.3 TSPC全加器對於BP-DTMOS/MTCMOS、HVT、LVT在最小CLK操作速
度下功率消耗比較結果................................38
2.5 結論..................................................39
Chapter3 BP-DTMOS/MTCMOS 技術之單一相位時序乘法器電路 (TSPC
Multiplier Circuit)..............................40
3.1 BP-DTMOS/MTCMOS TSPC Multiplier 電路..................41
3.1.1 BP-DTMOS/MTCMOS TSPC Multiplier 架構................41
3.1.2 Carry Look Ahead Chain 電路圖.......................42
3.2 BP-DTMOS/MTCMOS TSPC Multiplier 電路分析模擬..........43
3.2.1 BP-DTMOS/MTCMOS、HVT、LVT乘法器在相同CLK操作速度下功率
消耗比較結果........................................45
3.2.2 BP-DTMOS/MTCMOS、HVT、LVT乘法器在最小CLK操作速度下功率
消耗比較結果........................................46
Chapter4 結論和未來方向(Conclusion and Future Work).......47
參考文獻......................................48
參考文獻
[1] J.B. Kuo, "Low-Voltage SOI CMOS Devices and
Circuits, " Wiley, New York (2004)

[2] J.B. Kuo, J. Lou, "Low-Voltage CMOS VLSI Circuits,"
Wiley, New York,1999.

[3] J.B. Kuo, "CMOS Digital IC," McGraw-Hill, Taiwan,
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[4] Shen, E, Kuo, J. B, “0.8V CMOS CAM Cell Circuit
with a Fast Tag-Compare Capability Using Bulk PMOS
Dynamic-Threshold (BP-DTMOS) Technique Based on
Standard CMOS Technology for Low-Voltage VLSI
Systems,”IEEE International Symp. Circuits and
Systems Proc, IV 583-586 (2002)

[5] Shen, E, J.B. Kuo, ”A Novel 0.8V BP-DTMOS Content
Addressable Memory Cell Circuit Derived form SOI-DTMOS
Techniques, ” IEEE Conf Elec Dev and Solid State
Ckts, pp.243-245 (2003)

[6] Y. Ji-Ren, I. Karlsson, C. Svensson, “A True Single-
Phase-Clock Dynamic CMOS Circuit Technique,” IEEE
JSSC, vol.SC-22, 1987, pp.

[7] J. Yuan and C. Svensson, “High-speed CMOS circuit
technique,”IEEE J. Solid-State Circuits, vol. 24,
pp. 62–70, Feb. 1989.

[8] A. P. Chandrakasan, S. Sheng and R. W. Brodersen
“Low-power CMOS digital design” IEEE J. Solid-State
Circuits., vol. 27, no. 4, Apr, 1992.

[9] C. Svensson and A. Alvandpour, “Low power and low
volatage CMOS digital circuit techniques,” in Proc.
Low Power Electronics and Design, pp7-10, 1998.
[10] Alain Guyot and Selim Abou-Samra,”Low power CMOS
Ditital Design,”in Microelectronics, 1998. ICM ''98.
Proceedings of the Tenth International Conference
on ,pp. IP6- I13, 1998.

[11] N.F. Goncalves and H.J. DeMan,“NORA:A Racefree
Dynamic CMOS Technique for Pipeline Logic
Structure,” IEEE J. Sol. St. Ckts., 18(3),
261-266 (1983).

[12] "Hardware algorithms for parallel multiplication,"
http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html.

[13] I. S. Hwang and A. L. Fisher, “Ultrafast Compact 32- bit CMOS Adders in Multiplier-Output Domino Logic,”
IEEE J. Sol. St. Ckts., 24(2),358-369 (1989).
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