臺灣博碩士論文加值系統

本論文提出四種組合型電路與掃描鏈短路型錯誤的模組，這種短路型錯誤的一端是屬於組合型電路，而另一端屬於掃描鏈。根據實驗結果顯示，此種組合型電路與掃描鏈短路型錯誤有別於所有已知的錯誤，而是會受到掃描進入的影響。本論文使用一個鄰近電路配對擷取演算法去利用電路的實體設計布局快速找出可能發生短路的相鄰電路組。本論文提出兩組結構化簡技巧快速去除不可能的電路組以增進程式執行速度。在ISCAS’89基準電路的實驗顯示，平均而言對組合型電路與掃描鏈短路型錯誤的診斷結果準確率為最多四組鄰近電路配對。當錯誤資料相當有限時，本論文提出的技術仍然十分有效。本論文展示了以軟體診斷組合型電路與掃描鏈短路型錯誤的可能性。

This thesis proposes four logic-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-chain bridging faults, unlike existing scan chain fault models, depend on the previous scan inputs as well as primary inputs. A bridging pair extraction algorithm is proposed to quickly extract bridging pairs from the layout. The paper proposed two sets of structural reduction techniques so that run time is very short. Experimental results on ISCAS benchmark circuits show that, on the average, logic-chain bridging faults can be diagnosed within an accuracy of four bridging pairs. The techniques are still applicable when there are only ten failing patterns due to limited ATE failure memory. This paper demonstrates the feasibility to diagnose logic-chain bridging faults by software.

摘要 i
Abstract ii
Table of Contents iii
List of Figures v
List of Tables vi
List of Techniques vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Proposed Technique 3
1.3 Contribution 5
1.4 Organization 6
Chapter 2 Background 7
2.1 Fault Model 7
2.1.1 Scan Chain Fault Model 7
2.1.2 Logic-chain Bridging Fault Model 11
2.2 Past Research 16
2.2.1 Scan Chain Fault Diagnosis 16
2.2.2 Logic Bridging Fault Diagnosis 23
2.3 Bridging Pair Extraction (BPE) 26
Chapter 3 Proposed Techniques 28
3.1 Assumption 28
3.2 Overall Diagnosis Flow 29
3.3 Static Reduction 30
3.4 Dynamic Reduction 38
3.5 Fault Simulation 51
3.5.1 Fault Injection 51
3.5.2 Parallel Simulation Technique 53
3.6 Scoring and Ranking 55
3.7 Time and Space Complexity Analysis 56
3.7.1 BPE Time and Space Complexity Analysis 57
3.7.2 Reduction Techniques Time and Space Complexity Analysis 57
3.7.3 Fault Simulation Run Time Analysis 57
Chapter 4 Experimental Results 59
4.1 Testcase Generation 59
4.2 BPE Experimental Results 60
4.3 Four Models Diagnosis Results 61
4.4 Comparison with intermittent fault diagnosis 64
4.5 Comparison with Liu’s work 65
Chapter 5 Discussion and Future work 67
5.1 Accuracy 67
5.1.1 Bridging Pair Extraction (BPE) 67
5.1.2 Scoring 68
5.2 Scalability 68
5.3 Multiple Faults 69
5.4 Macro Fault 70
Chapter 6 Summary 71
References 72

[Acken 92] J.M. Acken and S.D. Millman, “Fault Model Evolution For Diagnosis: Accuracy vs Precision,” Proc. of IEEE Custom Integrated Circuits Conference, 1992.
[Chakravarty 93] S. Chakravarty and Y. Gong, “An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits, ” Proc. Design Automation Conf., pp520-524, 1993.
[Chess 95] B. Chess, D. Lavo, and T. Larabee, “Diagnosis of Realistic Bridging Faults with Single Stuck-at Information, “ Proc. IEEE Int’l Test Conf., 1995.
[Chuang 08] Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, and James Chien-Mo Li, “Diagnosis of Multiple Scan Chain Timing Faults, “ IEEE Trans. On Computer-Aided Design, vol.27, no.6, pp.1104-1116, 2008.
[De 95] Kaushik De, Arun Gunda, “Failure Analysis for Full-Scan Circuits,” Proc. IEEE Int’l Test Conf., pp. 636-645, 1995
[Edirisooriya 95] S. Edirisooriya and G. Edirisooriya, “Diagnosis of Scan Path Failures,” Proc. IEEE VLSI Test Symp., pp. 250-255, 1995.
[Ferguson 88] F. J. Ferguson and J. P. Shen, “Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis,” Proc. IEEE Int’l Test Conf., pp. 475-484, 1988.
[Guo 01] R. Guo and S. Venkataraman, “A Technique for Fault Diagnosis of Defects in Scan Chains,” Proc. IEEE Int’l Test Conf., pp. 268-277, 2001.
[Guo 02] R. Guo and S. Venkataraman, “A New Technique for Scan Chain Failure Diagnosis,” Proc. Int’l Symp. Testing and Failure Analysis, pp. 723-732, 2002.
[Hirase 99] J. Hirase, N. Shindou, and K. Akahori, “Scan Chain Diagnosis Using IDDQ Current Measurement,” Proc. Asian Test Symp. pp. 153-157, 1999.
[Huang 03] Y. Huang, W.-T. Cheng, S. M. Reddy, C.-J. Hsieh, and Y.-T. Hung, “Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault,” Proc. IEEE Int’l Test Conf., pp. 319-327, 2003.
[Huang 04] Y. Huang, W.-T. Cheng, C.-J. Hsieh, H.-Y. Tseng, A. Huang, and Y.-T. Hung, “Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis”, Proc. IEEE Design Automation & Test in Europe Conf., pp. 1530-1591, 2004.
[Huang 04] Y. Huang, W.T. Cheng, and K. H. Tsai, “Diagnosing DACS (Defects That Affect Scan Chain and System Logic),” Proc. Int’l Symp. for Testing and Failure Analysis, pp. 191-196, 2004.
[Huang 06] Y. Huang, W.-T. Cheng, N. Tamarapalli, J. Rajski, and R. Klingenberg, “Diagnosis with Limited Failure Information,” Proc. Int’l Tes Conf., Oct. 2006.
[Huang 07] Y. Huang, “Dynamic Learning Based Scan Chain Diagnosis,” Proc. Design and Test in Europe, pp.510-515, 2007.
[Huang 07i] Y. Huang, W. Hsu, Y-S. Chen, W. T. Cheng, R. Guo, “Diagnose Compound Scan Chain and System Logic Defects,” Proc. IEEE Int’l Test Conf., 2007.
[Huang 08] Y. Huang, R.-F. Guo, W.-T. Cheng, and James C.-M. Li, “Survey of Scan Chain Diagnosis,” IEEE Design & Test of Computers, 2008 (to appear).
[Huisman 05] Leendert M. Huisman, data mining and diagnosis of IC fail, Springer Science, 2005.
[ITRS 2007] International Technology Roadmap for Semiconductors, http://www.itrs.net/
[Kao 06] Yu-Long Kao, Wei-Shun Chuang, and J. C-M Li, “Jump Simulation: A Fast and Precise Scan Chain Fault Diagnosis Technique, “Proc. IEEE Int’l Test Conf., Oct. 2006.

[Kibarian 05] J. Kibarian, “The Nature of Yield Ramping: Keeping Ahead of Evolution,” keynote speech, IEEE Int’l Test Conference, 2005.
[Koenemann 04] B. Koenemann, “Test In the Era of "What You see Is NOT What You Get”, " keynote speech, IEEE Int’l Test Conference, 2004.
[Koren 96] I. Koren, Z. Koren, and C. H. Stapper, ”A statistical study of defect maps of large area VLSI IC''s,” IEEE Trans. VLSI Syst., vol.2, no.2, pp.249-56, 1996.
[Kruseman 04] B. Kruseman, A. Majhi, C. Hora, S. Eichenberger, and J. Meirlevede, “Systematic Defects in Deep Sub-Micron Technologies,” Proc. IEEE Int’l. Test Conf., pp. 290-298, 2004.
[Kundu 94] S. Kundu, “Diagnosis Scan Chain Faults,” IEEE Trans. VLSI Syst., pp. 512-516, 1994.
[Lavo 96] D. Lavo and T. Larabee, “Beyond the byzantine generals: unexpected behavior and bridging fault diagnosis, “ Proc. IEEE Int’l Test Conf., 1996.
[Lee 91] H. K. Lee and D. S. Ha, “On the Generation of Test Patterns of Combinational Circuits,” Technical Report, No 12-93, Dept. of Electrical Eng. Virginia Polytechnic Institute and State University, 1991.
[Lee 08] King Leong Lee; Basturkmen, N.Z.; Venkataraman, S, “Diagnosis of Scan Clock Failures, “ Proc. IEEE VTS., pp.67-72, 2008.
[Li 00] J. C-M Li and E. J. McCluskey, “Testing and Diagnosis of Stuck and Resistive Open Defects, “ Proc. Int’l Test Conf., Oct. 2000.
[Li 05a] J. C.-M. Li, “Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains, “ IEEE Trans. on VLSI Systems, Vol.13, No. 6, June, 2005, pp. 708-718.
[Li 05b] J. C.-M. Li, “Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains,” IEEE Trans. on Computers, Vol. 54, No. 11, 2005, pp. 1467-1472.
[Liu 08] W. C. Liu, Diagnosis of Logic-Chain Bridging Faults, Master Thesis, National Taiwan University, 2008.
[Makar 95] S. Makar and E. J. McCluskey, “Functional Tests for Scan Chain Latches”, Proc. IEEE Int’l Test Conf., pp.606-615, 1995.
[Mei 74] KCY Mei, “Bridging and Stuck-at faults”, IEEE Trans. on Computers, 1974
[Mentor 07] Mentor Graphics Corporation, YeildAssist User’s Guide, Software Version 8.2007_2, May 2007.
[Metra 93] C. Metra, M. Favalli, P. Olivo, B. Ricco, “Testing og Resistive Bridging Faults in CMOS Flip-flops,” Proc. Eur. Test Conf., pp530-531, 1993.
[Millman 90] S. D. Millman, E. J. McCluskey, and J. M. Acken, “Diagnosing CMOS Bridgmg Faults with Stuck-at Fault Dictionaries, ” Proc. IEEE Int’l Test Conf., pp. 860-870, 1990.
[Motika 03] F. Motika, P. Nigh, P. Song, and H. B. Druckerman, “AC Scan Diagnostic Method,“ U.S. Patent 6,516,432 B1, Feb. 4, 2003.
[Narayanan 97] S. Narayanan and A. Das, “An Efficient Scheme to Diagnose Scan Chains,” Proc. IEEE Int’l Test Conf., pp.704-713, 1997.
[Nigh 98] P. Nigh, D. Vallett, A. Patel, and et. al., “Failure Analysis of Timing and IDDq Failures from the SEMATECH Test Methods Experiment,“ Proc. IEEE Int’l. Test Conf., pp.43-52 , 1998.
[Pradhan 86] D. K. Pradhan (editor), Fault Tolerant Computing: Theory and Techniques, Prentice Hall, 1986.
[Schafer 92] J. Schafer, F. Policastri and R Mcnulty, “Partner SRLs for Improved Shift Register Diagnostics,” Proc. IEEE VLSI Test Symp., pp. 198-201, 1992.
[Sebeke 95] C. Sebeke, J.P. Teixeira, and M.J. Ohletz, “Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits,” Proc. European Design and Test Conf., 464 1995.
[Sharma 07] M. Sharma, W-T. Cheng, T-P. Tai, Y-S. Cheng, W. Hsu, C. Liu, SM. Reddy, and A. Mann, “Faster Defect Localization in Nanometer Technology Based on Defective Cell Diagnosis,” Proc. IEEE Int’l Test Conf., 2007.
[Song 04] P. Song, F. Stellari, T. Xia, and A. Weger, “A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current,” Proc. IEEE Int’l. Test Conf., pp. 140-147, 2004.
[Stanley 01] K. Stanley, “High-Accuracy Flush-and-scan Software Diagnostic,” IEEE Des. Test. Comput., pp. 56-62, Nov-Dec, 2001.
[Stanojevic 01] Z. Stanojevic and D. M. H. Walker, “FedEx-A Fast Bridging Fault Extractor, “ Proc. IEEE Int’l Test Conf., pp.696-703, 2001.
[Stellari 04] Stellari, F.; Weger, A.J.; Peilin Song; McManus, M.K, “Dynamic latchup study using transmission line pulses and picosecond imaging circuit analysis [CMOS IC latchup],” Proc. ESSDERC, pp.205-208, 2004.
[Tzeng 07] C.-W. Tzeng and S.-Y. Huang, “Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in A Scan Chain,” IEEE Trans. on Circuit and Systems II, vol.54, no. 5, 2007.
[Venkataraman 97] S. Venkataraman and K. Fuchs, “A Deductive Technique for Diagnosis of Bridging Faults, “ Proc. Int’l Conf. on Computer-Aided Design, pp.562-567, 1997.
[Vogels 03] T. Vogels, W. Maly, and R. D. Blanton, “Progressive Bridge Identification,” Proc. IEEE Int’l Test Conf., pp.309-317, 2003.
[Wang 06] Luang-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, VLSI Test Principles and Architectures: Design for Testability, Elsevier Science, July 2006.
[Wu 98] Y. Wu, “Diagnosis of Scan Chain Failures,” Int’l Symp. On Defect and Fault Tolerance in VLSI systems, pp. 217-222, 1998.
[Yang 05] J.-S. Yang and S.-Y. Huang, “Quick Scan Chain Diagnosis Using Signal Profiling, “ Proc. Int’l Conf. on Computer Design, Oct. 2005.
[Yang 09] F. Yang, S. Chakravarty, N. Prasanna, S. M. Reddy, I. Pomeranz, “Detectability of Internal Bridging Faults in Scan Chains,” Proc. Asian and South Pacific Design Automation Conf., pp.678-683, 2009.
[Zou 05] W. Zou, W. T. Cheng, and S. M. Reddy, “Bridge Defect Diagnosis with Physical Information, “ Proc. IEEE Asian Test Symp., 2005.