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研究生:錢膺仁
研究生(外文):Ying-Ren Chien
論文名稱:以10GBASE-T為例之全雙工多通道基頻預編碼系統強健性設計
論文名稱(外文):Robust Transceiver Design for Full-duplex Multichannel Baseband Tomlinson-Harashima Precoded 10GBASE-T Systems
指導教授:曹恆偉曹恆偉引用關係
指導教授(外文):Hen-Wai Tsao
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電信工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:134
中文關鍵詞:經銅線傳輸之百億位元乙太網路(10GBASE-T)湯林森-何洛緒瑪預編碼多通道時脈回復時脈誤差偵測遠端串音干擾消除非同步等化
外文關鍵詞:10GBASE-TTomlinson-Harashima PrecodingMulti-channel Symbol Timing RecoveryTiming Error DetectorFEXT CancellationAsynchronous Equalization
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在高速通訊系統中,多輸入多輸出 (Multi-input multi-output, MIMO) 技術已被廣泛使用於增加資料傳輸率,10GBASE-T系統即為此技術之應用實例。 此系統是一個全雙工多通道之基頻預編碼系統,其中預編碼技術是採用湯林森-何洛緒瑪預編碼 (Tomlinson-Harashima precoding, THP)。 在10GBASE-T系統中,對抗通道變化的強健性收發機設計的挑戰是通道之交互關聯性 (channel-interdependence)、迴路交互干擾 (loop-interaction)以及預等化器本身之非線性特性。 再者,因系統之資料傳輸率高達每秒百億位元,致使系統之雜訊容忍裕度 (noise-margin) 以及時脈回復裕度 (timing-margin) 均相對嚴苛,所以設計強健性的等化以及時脈回復機制是個重大的挑戰也是個重要的議題。
在本論文中,我們分析了當傳送端的通道訊息 (channel state information, CSI) 是不完整的情況下,使用固定預編碼器係數對於資料傳輸模式中,接收端的決策點訊噪比 (decision-point signal-to-noise ratio, DP-SNR) 之影響,並且提出了包含可適性接收 (adaptive reception) 與多通道符元時脈回復架構 (multichannel symbol timing recovery, MC-STR)。 針對可適性接收,我們提出了一種可適性「兩段式等化及遠端串音干擾消除 (two-stage equalization and FEXT cancellation, TS-EFC)」架構,此設計可以讓收發機在不更新預等化器係數的前提之下,能夠有效對抗通道變異。 在第一階段,我們提出在傳送端使用一個非決策導向的遠端串音干擾消除器以避免錯誤蔓延的問題。 在第二階段,我們設計了一個可適性的多輸入多輸出等化器,再搭配一個預處理單元,使得接收端可以對抗殘餘錯誤。 針對多通道符元時脈回復架構,我們提出了一種稱為「平均取樣相位 (averaged sampling phase, ASP)」的架構,此架構可以降低由於不完整的通道訊息所造成的雜訊以及由於通道之交互關聯性所引入之雜訊。 再者,我們提出了一個相對應的「三相時脈復原策略 (three-phase timing strategy)」以降低迴路交互干擾並且可以使得時脈誤差偵測器在訓練模式與資料傳輸模式均擷取出正確的時脈誤差資訊。 在資料傳輸模式中,我們設計了一種「基於有效資料序列的時脈誤差偵測器」,它利用存在於有效資料序列之間的自相關性,使得隱藏在已編碼訊號中的時脈錯誤訊息可以被萃取出來。 此平均取樣相位的架構也可以應用於非迴路定時 (non-loop-timed) 之架構。 另外,我們也討論了在非迴路定時的架構中,其迴路延遲 (loop delay) 之議題,並且提出了一種可以降低迴路延遲的接收機架構,不過付出的代價是要使用較複雜的「非同步延遲式最小均方 (asynchronous delayed least mean square, AD-LMS)」適應演算法作為等化器係數調整之用。
模擬結果顯示我們的可適性兩段式等化及遠端雜訊消除架構可有效對抗通道變異,並且大幅提升決策點訊噪比。此架構可消除錯誤蔓延並提高可適性演算法調整的收斂速度;再者,平均取樣相位的方式不僅可以降低時脈抖動 (timing jitter) 達50%並且當四對傳輸線對中若僅有某些線對受到不完整通道訊息的影響,可提升決策點之訊噪比高達1.40dB;相較於傳統的時脈誤差偵測器,我們所提出的「基於有效資料序列的時脈誤差偵測器」可達到較低的峰對峰時脈抖動值 (peak-to-peak jitter) 以及較高的時脈誤差偵測增益 (TED gain)。
Multi-input multi-output (MIMO) techniques have been used to increase the data rate in high-speed communication systems. One of the successful applications is the 10GBASE-T system which is a full-duplex multichannel baseband system using Tomlinson-Harashima (TH) precoding (THP) techniques. The challenges to design a robust transceiver against the channel variation for 10GBASE-T are the channel-interdependence, loop-interaction and nonlinearity associated with the THP. Moreover, for the system with data transmission rate of 10Gbps, both the noise-margin and timing-margin become much tighter. Therefore, a robust design of equalization and timing recovery mechanisms is crucial and critical.
In this dissertation, we analyze the impact of fixed-coefficient THP on the decision-point signal-to-noise ratio (DP-SNR) in the presence of imperfect channel state information (CSI) and propose a solution of the robust transceiver architecture which includes adaptive reception and multichannel symbol timing recovery (MC-STR) architectures. For adaptive reception, we propose an adaptive two-stage equalization and far-end crosstalk (FEXT) cancellation (TS-EFC) without updating the THP coefficients to combat the channel variation at both transmitter and receiver sides. In the first stage, we propose a new non-decision-directed FEXT canceller at the transmitter side to avoid error propagation. In the second stage, we devise an adaptive MIMO equalizer together with a novel pre-processing unit at the receiver side to combat the residual errors. For MC-STR systems, we propose a better scheme called the averaged-sampling-phase (ASP) which reduces the noise caused by an imperfect CSI and interference induced among multiple channels. Moreover, an associated three-phase timing strategy is also proposed to mitigate the loop-interaction and to extract correct timing error information during both training and data modes. In the data mode, we devise an effective data sequence based timing error detector (EDS-TED) which exploits the autocorrelation between EDS signals so that the embedded timing error information can be extracted out. Similar methodology can also be applied on non-loop-timed implementations. We discuss the loop delay concerns for the non-loop-timed implementation and propose a receiver architecture in which the loop delay is reduced at the price of adopting a more complicated asynchronous delayed least mean square (AD-LMS) algorithm for equalizer adaptations.
Simulation results show that our TS-EFC architecture is robust against to channel variation and significantly improves the DP-SNR. It eliminates the error propagation and also achieves faster convergence rate during adaptation process; moreover, the proposed ASP scheme reduces not only the timing jitter by 50% but also improves the DP-SNR by up to 1.40 dB in the presence of imperfect CSI on some channels of the multichannel; the proposed EDS-TED achieves the best performance, compared to the conventional TEDs, in terms of the resultant peak-to-peak jitter and TED gain.
List of Figures xiii
List of Tables xvii
List of Abbreviations xix
1 Introduction 1
1.1 Motivations and Challenges . . . . . . . . . . . . . . . . . . . . . 1
1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 THP-equalization and interference cancellation approaches 4
1.2.2 MC-STR approaches . . . . . . . . . . . . . . . . . . . . . 6
1.2.3 Loop-interaction solutions . . . . . . . . . . . . . . . . . . 6
1.2.4 TED designs . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Dissertation Organization . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Full-duplex Multichannel Baseband Tomlinson-Harashima Pre-coded Systems 17
2.1 Overview of 10GBASE-T . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.1 General Transceiver Architecture . . . . . . . . . . . . . . 19
2.1.2 Double Square 128 (DSQ128) Modulation and the proposed hypothesis-based decision rule . . . . . . . . . . . . . . . . 19
2.1.3 Tomlinson-Harashima Precoding . . . . . . . . . . . . . . . 23
2.1.4 Channel Impairments . . . . . . . . . . . . . . . . . . . . . 27
2.1.5 Supported Timing Recovery Configurations . . . . . . . . 32
2.1.6 Startup Procedure . . . . . . . . . . . . . . . . . . . . . . 35
2.2 System Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.1 Transmitted signal model . . . . . . . . . . . . . . . . . . 37
2.2.2 MIMO channel model . . . . . . . . . . . . . . . . . . . . 38
2.2.3 Received signal model . . . . . . . . . . . . . . . . . . . . 39
3 Robust Two-Stage Equalization and FEXT Cancellation Design 43
3.1 Issues with the Fixed THP and Channel-interdependence . . . . . 43
3.2 Proposed Two-Stage Approach . . . . . . . . . . . . . . . . . . . 46
3.2.1 Stage-1: Transmitter-side pre-compensation . . . . . . . . 46
3.2.2 Stage-2: Receiver-side post-compensation . . . . . . . . . . 50
3.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3.1 The effect of the TS channel on DP-SNR . . . . . . . . . . 55
3.3.2 The effect of TS and GM channels on DP-SNR . . . . . . 58
3.3.3 The effect of BLMS adaptive algorithm on SER . . . . . . 60
4 Analysis of Timing Error Detectors 63
4.1 Review of TED . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2 TH Precoded System Model . . . . . . . . . . . . . . . . . . . . . 65
4.3 Proposed EDS-based TED . . . . . . . . . . . . . . . . . . . . . . 67
4.3.1 Timing function analysis for the EDS-TED . . . . . . . . . 69
4.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.4.1 Open Loop Characteristics Comparisons . . . . . . . . . . 70
4.4.2 Closed Loop Performance Comparisons . . . . . . . . . . . 73
5 Proposed Robust MC-STR Design 77
5.1 Averaged-Sampling-Phase Scheme . . . . . . . . . . . . . . . . . . 79
5.1.1 Proposed cross-correlation-based sampling frequency offset (SFO) estimation algorithm . . . . . . . . . . . . . . . . . 82
5.1.2 Hybrid STR architecture design . . . . . . . . . . . . . . . 85
5.1.3 Analysis with phase-domain linear model . . . . . . . . . 87
5.2 Three-phase Timing Recovery Strategy . . . . . . . . . . . . . . . 90
5.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.1 Simulation Parameters . . . . . . . . . . . . . . . . . . . . 93
5.3.2 Convergence results and jitter comparisons . . . . . . . . . 93
5.3.3 Robustness comparisons with different STR schemes . . . 97
6 All-Digital Approach Consideration 103
6.1 Proposed Reduced Loop Delay Approach . . . . . . . . . . . . . . 105
6.1.1 The design of SRC and ISRC . . . . . . . . . . . . . . . . 105
6.1.2 Design of Interaction-free Loops . . . . . . . . . . . . . . . 109
6.1.3 Proposed AD-LMS Adaptation Algorithm . . . . . . . . . 109
6.1.4 Timing Recovery Scheme . . . . . . . . . . . . . . . . . . . 110
6.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7 Conclusions 117
7.1 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
A Symbol error rate analysis 123
B The detailed derivation of EDS-TED 125
Bibliography 127
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