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研究生:陳科璁
研究生(外文):Ke-Tsung Chen
論文名稱:5-MHz訊號頻寬320-MHz連續時間型三角積分調變器設計
論文名稱(外文):Design of a 320-MHz Continuous-Time Delta-Sigma Modulator with 5-MHz Signal Bandwidth
指導教授:李泰成
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:93
中文關鍵詞:類比數位轉換連續時間單位元量化寬頻分碼多工擷取電流控制超取樣三角積分調變器
外文關鍵詞:Analog-to-digital conversioncontinuous-timesingle-bit quantizationWCDMAcurrent-steeringoversamplingdelta-sigma modulator
相關次數:
  • 被引用被引用:1
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  • 收藏至我的研究室書目清單書目收藏:3
  隨著3G時代的來臨,從短距離到動輒數百公里的無線電資料與語音傳輸技術不斷地進展,使得無線行動通訊在人類生活中扮演相當重要的角色。由於高輸入動態範圍、高傳輸速率與低功率的需求,使得設計類比數位轉換器(ADCs)也必須達到較高解析度、頻寬與低功率的規格方能滿足這些嚴苛條件外,也可寬鬆無線接收器類比前端(analog front-end)電路部份的設計要求。

  本論文在系統層面設計上,著重於電路延遲效應補償的介紹以及時脈抖動的研究;在電路層面設計上,透過仔細地分析、推導與模擬,針對元件非理想效應來取捨評估元件規格。論文主要應用於寬頻分碼多工擷取(WCDMA)無線電通訊上,電路實現在訊號頻寬5-MHz,操作在320-MHz取樣頻率(即過取樣率為32)上之一位元量化三階低通連續時間型三角積分類比數位資料轉換調變器(delta-sigma A/D modulator)。量測結果達56-dB動態範圍(dynamic range)與最大SNR值51.3-dB(相當於8.2-bit有效位元)。利用2P4M 3.3-V台積電CMOS 0.35-μm製程與R-C積分器技術,電流功率消耗13.6-mA。
  With the advent of the third-generation (3G) era, wireless technologies on data and sounds transmission ranging from short distances to even hundreds of kilometers at its constant advances have had mobile telecommunications to be a quite important role in human life. Due to the demand for high input dynamic range, data rate, and low power, designing analog-to-digital (A/D) data converters must achieve not only the stringent conditions of higher resolution, higher bandwidth, and low power consumption, but also relax the requirements for the analog front-end parts of radio receivers.

  This thesis on system-level design focuses on introduction to the compensation of circuit-delayed effects and research to clock jitter; on circuit-level design it shows a better trade-off estimate on specifications through carefully analyzing, deriving out, and simulating the nonideal effects of circuit elements. The proposed implementation of the single-bit third-order low-pass continuous-time delta-sigma analog-to-digital (A/D) modulator can be mainly applied for wideband-code-division-multiple-access (i.e., so-called WCDMA) radio communications with 5-MHz signal bandwidth at sampling frequency of 320-MHz. Experimental results show that a signal-to-noise ratio (SNR) of 51.3dB (i.e., 8.2-bit ENOB) and a dynamic range of 56dB in the 2P4M 3.3-V TSMC CMOS 0.35-μm process with a R-C integrator topology. The measured current consumption is 13.6-mA.
誌  謝 ....................................................................................................................... I
中文摘要 .................................................................................................................... III
英文摘要 ..................................................................................................................... V
圖 目錄 ..................................................................................................................... X
表 目錄 ................................................................................................................. XIV


第一章 緒論 ................................................................................................................ 1
1.1 研究動機 .............................................................................................. 1
1.2 論文貢獻 .............................................................................................. 3
1.3 論文組織 .............................................................................................. 3

第二章 Sigma-Delta(ΣΔ)三角積分調變器概論 ................................................... 5
2.1 性能衡量標準 ...................................................................................... 5
2.1.1 SNR / SNDR / SFDR ............................................................ 5
2.1.2 動態範圍(Dynamic Range)................................................. 6
2.1.3 量化雜訊(Quantization Noise)............................................ 7
2.1.4 過取樣率(Oversampling Ratio)........................................... 9
2.1.5 雜訊移頻(Noise-Shaping).................................................. 10
2.2 ΣΔ ADC系統 ...................................................................................... 11
2.3 ΣΔ調變器的基本架構 ....................................................................... 13
2.3.1 一階ΣΔ調變器 .................................................................... 13
2.3.2 二階ΣΔ調變器 .................................................................... 15
2.3.3 高階ΣΔ調變器 .................................................................... 16
2.3.4 CIFB架構 ............................................................................. 17
2.3.5 CIFB與CIFF架構比較 ....................................................... 18
2.3.6 MASH架構 .......................................................................... 20
2.4 ΣΔ調變器的零點分佈最佳化 ........................................................... 22
2.5 ΣΔ調變器的穩定法則 ....................................................................... 24

第三章 ΣΔ調變器之迴路濾波器設計 ..................................................................... 25
3.1 傳統離散時間(DT)型ΣΔ調變器之迴路濾波器設計方法 ......... 25
3.2 連續時間(CT)型ΣΔ調變器之迴路濾波器設計方法 ................. 27
3.3 介紹Sliding Mode理論設計CT ΣΔ調變器 ................................... 31
3.4 DT與CT ΣΔ調變器的優缺點比較 ................................................ 34

第四章 系統層面設計與元件非理想性 .................................................................. 37
4.1 系統層面設計 .................................................................................... 37
4.2 運算放大器(OPAmp)的非理想效應 ........................................... 44
4.2.1 有限的OPAmp增益頻寬積對調變器的影響 ................... 44
4.2.2 有限的OPAmp迴轉率對調變器的影響 ........................... 47
4.2.3 有限的OPAmp增益對調變器的影響 ............................... 48
4.3 時脈抖動 ................................................................................. 49
4.3.1 時脈抖動對於DT ΣΔ調變器的影響 ................................ 50
4.3.2 時脈抖動對於CT ΣΔ調變器的影響 ................................ 51
4.4 迴路濾波器係數變異的影響 ............................................................ 53

第五章 電路設計與實現 .......................................................................................... 56
5.1 以理想電路元件實現的架構 ............................................................ 56
5.2 實際電路元件的設計 ........................................................................ 61
5.2.1 偏壓電路 .............................................................................. 62
5.2.2 運算放大器 .......................................................................... 64
5.2.3 類比數位轉換器DACs ........................................................ 66
5.2.4 比較器(一位元量化器).................................................... 67
5.2.5 D-Latch與時脈產生器 ........................................................ 71
5.3 整體電路模擬的結果 ........................................................................ 72

第六章 電路佈局與晶片測試 .................................................................................. 74
6.1 電路佈局與模擬 ................................................................................ 74
6.2 量測環境與結果 ................................................................................ 81
6.2.1 測試板設計 .......................................................................... 82
6.2.2 測試環境裝備 ....................................................................... 82
6.2.3 量測結果 ............................................................................... 84
6.2.4 相關文獻比較 ....................................................................... 86

第七章 結論與未來展望 .......................................................................................... 88
7.1 結論 .................................................................................................... 88
7.2 未來展望 ............................................................................................ 88

參考文獻 ...................................................................................................................... 90
[1] C. Ting, “An Audio Analog-to-Digital Converter with Wide Dynamic Range and
Low Distortion,” in National Taiwan Univerity, Master Thesis, Apr. 2008.
[2] Y. Shu, B. Song, and K. Bacrania, “A 65nm CMOS CT ΔΣ Modulator with 81dB
DR and 8MHz BW Auto-Tuned by Pulse Injection,” IEEE J. Solid-State Circuits,
pp. 500-501 & 631, Feb. 2008.
[3] Z. Li and T. S. Fiez, “A 14-Bit Continuous-Time Delta-Sigma A/D Modulator with
2.5-MHz Signal Bandwidth,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1873-
1883, Sep. 2007.
[4] R. Schoofs, M. S. J. Steyaert, and W. M. C. Sansen, “A Design-Optimized Continu-
ous-Time Delta-Sigma ADC for WLAN Applications,” IEEE Trans. Circuits Syst. I
, vol. 54, no.1, pp. 209-217, Jan. 2007.
[5] M. Tsai, “A Third-Order Multi-Bit Continuous-Time Delta-Sigma Modulator with
Incremental Data Weighted Averaging,” in National Taiwan Univerity, Master
Thesis, Jan. 2007.
[6] S. Pavan and N. Krishnapura, “Automatic Tuning of Time Constants in Continuous
Time Delta-Sigma Modulators,” IEEE Trans. Circuits Syst. II Expr. Briefs, vol. 54,
no. 4, pp. 308-312, Apr. 2007.
[7] F. Maloberti, Data Converters, Springer, 2007.
[8] K. Pun, S. Chatterjee, and P. R. Kinget, “A 0.5-V 74-dB SNDR 25-kHz Continuous
Time Delta-Sigma Modulator with a Return-to-Open DAC,” IEEE J. Solid-State
Circuits, vol. 42, no. 3, pp. 496-507, Mar. 2007.
[9] T. Lee, “Homework II of Advanced Analog Integrated Circuits,” GIEE course of
NTU in Taiwan, Mar. 2006.
[10] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 20-
mW 640-MHz CMOS Continuous-Time ΣΔ ADC with 20-MHz Signal Bandwidth
, 80-dB Dynamic Range and 12-bit ENOB,” IEEE J. Solid-State Circuits, vol. 41,
no. 12, pp. 2641-2649, Dec. 2006.
[11] H. Zare-Hoseini and I. Kale, “Clock-Jitter Reduction Techniques in Continuous-
Time Delta-Sigma Modulators,” IEEE International Symposium on VLSI DAT, pp.
1-2, Apr. 2006.
[12] S. Yu, “Analysis and Design of Single-Bit Sigma-Delta Modulators Using the The-
ory of Sliding Modes,” IEEE Trans. Control Syst. Tech. vol. 14, no. 2, Mar. 2006.
[13] W. Liu, “On Analysis of Continuous-Time Sigma-Delta ADC with Practical Consi-
derations,” in National Chiao-Tung Univerity, Master Thesis, Oct. 2006.
[14] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, IEEE
Press, Wiley & Sons, 2005.
[15] K. Nam, S. Lee, D. K. Su, and B. A. Wooley, “A Low-Voltage Low-Power Sigma-
Delta Modulator for Broadband Analog-to-Digital Conversion,” IEEE J. Solid-
State Circuits, vol. 40, no. 9, pp. 1855-1864, Sep. 2005.
[16] Y. Fujimoto, P. L. Ré, and M. Miyamoto, “A Delta-Sigma Modulator for a 1-Bit
Digital Switching Amplifier,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1865-
1871, Sep. 2005.
[17] M. Ortmanns, F. Gerfers, and Y. Manoli, “A Continuous-Time ΣΔ Modulator with
Reduced Sensitivity to Clock Jitter Through SCR Feedback,” IEEE Trans. Circuits
Syst. I, vol. 52, no. 5, pp. 875-884, May 2005.
[18] Y. Lin, “Novel Three-Level Modulation Technique for a Class-D Audio Amplifier,”
in National Sun Yat-sen Univerity, Master Thesis, Jul. 2005.
[19] E. H. Dagher, P. A. Stubberud, W. K. Masenten, M. Conta, and T. Dinh, “A 2-GHz
Analog-to-Digital Delta-Sigma Modulator for CDMA Receivers with 79-dB Sig-
nal-to-Noise Ration in 1.23-MHz Bandwidth,” IEEE J. Solid-State Circuits, vol. 39
, no. 11, pp. 1819-1828, Nov. 2004.
[20] N. Beilleau, H. Aboushady, and M. M. Louërat, “Filtering Adjacent Channel Bloc-
kers using Signal-Transfer-Function of Continuous-Time ΣΔ Modulators,” IEEE
Midwest Symp. Circuits Syst., vol. 1, pp. I - 329-332, Jul. 2004.
[21] S. Yan and E. Sánchez-Sinencio, “A Continuous-Time ΣΔ Modulator with 88-dB
Dynamic Range and 1.1-MHz Signal Bandwidth,” IEEE J. Solid-State Circuits, vol
. 39, no. 1, pp. 75-86, Jan. 2004.
[22] O. Bajdechi and J. H. Huijsing, Systematic Design of Sigma-Delta Analog-to-Digi-
tal Converters, Kluwer Academic Pub., 2004.
[23] M. Ortmanns, F. Gerfers, and Y. Manoli, “Compensation of Finite Gain-Bandwidth
Induced Error in Continuous-Time Sigma-Delta Modulators,” IEEE Trans. Circuits
Syst. I, vol. 51, no. 6, pp. 1088-1099, Jun. 2004.
[24] M. Ortmanns, F. Gerfers, and Y. Manoli, “A 1.5-V 12-bit Power-Efficient Continu-
ous-Time Third-Order ΣΔ Modulator,” IEEE J. Solid-State Circuits, vol. 38, no. 8,
pp. 1343-1352, Aug. 2003.
[25] M. S. Kappes, “A 2.2-mW CMOS Bandpass Continuous-Time Multibit Δ-Σ Band-
width for Wireless Applications,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp.
1098-1104, Jul. 2003.
[26] G. I. Bourdopoulos, A. Pnevmatikakis, V. Anastassopoulos, and T. L. Deliyannis,
Delta-Sigma Modulators – Modeling, Design, and Applications, Imperial College
Press, 2003.
[27] M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D Converter in 0.35μm CMOS,”
IEEE J. Solid-State Circuits, vol. 36, no. 12, pp.1847-1858, Dec. 2001.
[28] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., 2001.

[29] J. Ho, “On the Design and Test of Switched-Current Sigma-Delta Modulator,” in
National Yunlin University of Science & Technology, Master Thesis, Jun. 2001.
[30] E. Fogleman, J. Welz, and I. Galton, “An Audio ADC Delta-Sigma Modulator with
100-dB Peak SINAD and 102-dB DR Using a Second-Order Mismatch-Shaping
DAC,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 339-348, Mar. 2001.
[31] T. Burger and Q. Huang, “A 13.5-mW 185-Msample/s ΔΣ Modulator for UMTS/
GSM Dual-Standard IF Reception,” IEEE J. Solid-State Circuits, vol. 36, no. 12,
pp. 1868-1878, Dec. 2001.
[32] J. A. Cherry and W. M. Snelgrove, Continuous-Time Delta-Sigma Modulators for
High-Speed A/D Conversion, Kluwer Academic Pub., 2000.
[33] T. Kuo, K. Chen, and J. Chen, “Automatic Coefficients Design for High-Order Sig-
ma-Delta Modulators,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
, vol. 46, no. 1, Jan. 1999.
[34] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters:
Theory, Design, and Simulation, IEEE Press, New York, 1997.
[35] D. A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley & Sons, 1997.
[36] O. Shoaei, “Continuous-Time Delta-Sigma A/D Converters for High Speed Appli-
Cation,” in Carleton University, PHD Thesis, Nov. 1995.
[37] B. Razavi, Principles of Data Conversion System Design, Wiley & Sons, 1995.
[38] J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique,” IEEE J. Solid-
S tate Circuits, vol. 24, no. 1, pp. 62-70, Feb. 1989.
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