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研究生:吳龢峻
研究生(外文):Ho-Chun Wu
論文名稱:高壓N型金氧半電晶體對於源極與基極佈局參數對靜電放電特性的研究
論文名稱(外文):Study of Source and Body Contacts Layout Design to High Voltage NMOS ESD Protection Devices
指導教授:陳秋麟陳秋麟引用關係
指導教授(外文):Chen Chern-Lin
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:51
中文關鍵詞:高壓N型金氧半電晶體源極基極佈局參數
外文關鍵詞:High Voltage NMOS ESDSource ContactsBody ContactsLayout Design
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在本研究中,分析了高壓N型金氧半電晶體元件在靜電放電發生及元件在高電壓導通時的電流與電壓特性。靜電放電防護的旁通電晶體在應用於大尺寸的通道寬度時,必須以多指狀結構(multi-finger)來佈局(Layout),以提高旁通電晶體的佈局效益。然而由於N型金氧半電晶體具有明顯的驟回崩潰 (Snapback Breakdown) 特性,以及多指狀結構佈局上每一根相對於基體 (Substrate) 中N型橫向寄生雙載子電晶體與連接至基極的等效電阻之不同,在靜電放電衝擊下造成多指狀結構N型金氧半電晶體,不會同時導通來旁通此一靜電放電電流,卻是集中於部分指狀N型金氧半電晶體。此N型金氧半電晶體不均勻導通的現象使得靜電放電耐受度無法隨著增加元件通道寬度尺寸增大而線性增加,造成靜電放電防護電路設計的困難。
此篇論文主旨在改變源極與基極的佈局參數在多指狀結構N型金氧半電晶體。並據以找出高壓元件靜電放電最佳化的佈局規則。並增強其靜電放電耐受度。因此我們設計了不同佈局參數的元件,再利用傳輸線觸波產生器量測觀察其靜電放電均勻度。本研究實驗及分析的結果,可以作為未來高壓元件在更深入研究與設計時的重要依據。
This study analyzes the characteristic of ESD (electro-static-discharge) of high voltage NMOS (N-type metal oxide semiconductor) transistor current and voltage when NMOS is turned-on in high voltage. When the width of bypass MOS in the ESD protection circuit has to layout in the multi-finger type so as to decrease the layout area cost, in the mean while, due to the snapback breakdown of NMOS and the resistance connecting the base of the parasitic lateral bipolar transistor in the substrate is individually different. These sub-multi-finger NMOS’can not be turned on simultaneously. The ESD current is passed in few MOS’. The uniform turn-on of NMOS results in the endurance of ESD can increase as the width of protection device is increased. In this condition, it is more difficult to design an ESD protection circuit.
This thesis is trying to change the layout parameters of source and bulk of a multi-finger NMOS so as to find out optimal layout rules of a high voltage ESD protection device. Different layout parameter of NMOS’are tested. The uniformity of ESD devices are measured by transmission pulse generator. The results of this study can provide evidences for further study of high voltage ESD device.
第一章 緒論 1
1.1 研究背景與動機 1
1.2 內容簡介 3
第二章 積體電路靜電放電 4
2.1前言 4
2.2 靜電放電的模式及工業測試標準 6
2.2.1 人體放電模式 6
2.2.2 機器放電模式 7
2.2.3 元件充電模式 8
2.3 靜電放電的測試 9
2.4 積體電路靜電放電防護設計之基本概念 11
2.4.1 積體電路防護電路之設計概念 11
2.4.2 積體電路防護元件之選用 13
2.4.3 靜電放電防護電路的實例 15
第三章 金氧半積體電路之靜電放電防護技術 17
3.1 前言 17
3.2 製程上的改進方法 19
3.2.1 提升靜電放電耐受度佈植製程 19
3.2.2金屬矽化物擴散層分隔製程 22
3.3靜電放電防護金氧半場效電晶體佈局法則 27
第四章 高壓金氧半電晶體之靜電放電防護 30
4.1前言 30
4.2佈局差異及影響 31
第五章 實驗量測與結果分析 39
5.1實驗設定與偏壓 39
5.2 基極的寬度為參數的電流與電壓的測試結果 40
5.3對佈局參數基極與源極的距離為參數的電流與電壓測試結果 44
第六章 結論與展望 50
參考文獻 51
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[7]A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, 2nd Edition, New York: Wiley, 2002.
[8] Electrostatic discharge (ESD) sensitivity testing - human body model (HBM), EIA/JEDEC Standard Test Method A114-B, 2000.
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[13]T. Maloney and N Khurana, “Transmission Line Pulsing Techniques for Circuit Modeling”, EOS/ESD Symposium Proceedings, 1985, pp49-54
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[16] 0.5um HIGH VOLTAGE 2P3M POLYCIDE 40V/40V DESIGN RULES, Vanguard International Semiconductor Corporation
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