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研究生:游勝帆
研究生(外文):Shane-Feng Yu
論文名稱:硬體網路加速引擎
論文名稱(外文):Network Accelerator Engine
指導教授:王勝德王勝德引用關係
指導教授(外文):Sheng-De Wang
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:39
中文關鍵詞:硬體網路加速引擎EthernetOffloadFPGAThroughput
外文關鍵詞:Network Accelerator EngineEthernetOffloadFPGAThroughput
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在本論文中,我們提出硬體網路封包加速引擎(Network Accelerator
Engine),加速乙太網路(Ethernet Network)TCP/IP 通信協定層的處理速度。現行乙太網路的傳輸都是由CPU 來處理。經由乙太網路控制器(Ethernet MAC Controller),透過CPU 來處理網路上的資料傳輸,把資料從一台電腦傳輸到另一台電腦。利用TCP/IP 通信協定,以軟體方式處理時,需依靠CPU來做資料搬移、網路封包解析及處理系統中斷,因而消耗大量的CPU 運算能力。由於現行網路介面速度的提升,乙太網路的傳輸率由10/100Mbps 快速的成長至1G/10Gbps,更使CPU 無法負荷如此龐大的資料量處理,使得網路封包處理成為系統最大的效能瓶頸,網路封包加速引擎主要是將網路的傳輸的工作從CPU 分離出來,減少系統中斷、資料搬移及網路封包計算,所造成的系統損耗,以增進系統效能(Throughput)。以硬體方式將IP 資料封包從乙太網路控制器中傳給IP 層,藉由網路層卸載以減少CPU 處理TCP/IP 網路封包時,所耗損的系統資源。本論文在Altera Cyclone II FPGA Development Kit 之發展平台下,直接將快速乙太網路MAC 控制晶片與網路封包加速引擎連接,藉以改善系統效能,依據實驗結果,得到100Mbps 的網路速度。
Network Accelerator Engine
Abstract
The wired speed of the local area network has been increased from 10/100 Mbps to 1G/10
Gbps recently and deep packet inspections are required in real-time by firewall machines to secure
the Internet services. The processing of network packets has become the system’s major bottleneck.
Network accelerator engines can offload the computing need of CPU with a specific design
circuit. In this thesis, we design and implement a Network Accelerator Engine to accelerate the
processing speed of TCP/IP protocol stack in an embedded system. The proposed offload engine is
consisted of four modules, namely, Datagram Receiver Module, Network Accelerator Module,Checksum Module, and Access Control List Module. In the proposed offload engine, we directly retrieve packets from the media access controller (MAC) and parse them for IP headers and payload
without using any processor bus and interrupt.
In a result, the packet processing speed does not depend on any software or CPU architecture.In current implementation in an Altera Cyclone II platform, we can achieve the data throughput of 100Mbps, which is the wired speed of the system’s MAC.
論文審定書………………………………………………………………i
誌謝 ……………………………………………………………………ii
中文摘要………………………………………………………………iii
英文摘要…………………………………………………………………iv
目錄………………………………………………………………………v
圖目錄…………………………………………………………………vii
表目錄……………………………………………………………………ix
第一章 緒論 ……………………………………………………………1
1.1 研究動機 ……………………………………………………………1
1.2 研究目標與貢獻 ……………………………………………………1
1.3 章節概述 ……………………………………………………………2
第二章相關研究與技術 …………………………………………………3
2.1 TCP/IP卸載引擎 ……………………………………………………3
2.2 TCP/IP Functions With FPGA ……………………………………6
2.2.1 An Open TCP/IP Core for Reconfigurable Logic …………7
2.2.2 IPBlaze TOE Core ………………………………………………9
2.2.3 Seiko Epson S1S60000 ………………………………………10
2.3 TCP/IP Networking Communication Components ……………11
2.4 DM90000乙太網路控制器 …………………………………………12
第三章 網路封包加速引擎電路架構 …………………………………15
3.1電路架構 ……………………………………………………………15
3.2網路加速控制器 ……………………………………………………17
3.2.1封包控制模組 ……………………………………………………17
3.2.2乙太網路解析模組 ………………………………………………21
3.2.3網路解析模組 ……………………………………………………22
3.2.4 封包標頭核對總和模組 ………………………………………25
3.3 網路存取控管模組…………………………………………………26
第四章系統實作 ………………………………………………………27
4.1 Altera DE2 Development Tool Kit ……………………………27
4.2 電路模擬 …………………………………………………………29
4.3 Altera Quartus II ………………………………………………30
4-4 SignalTap …………………………………………………………31
第五章實驗結果 ………………………………………………………33
5.1 Synthesis Result ………………………………………………33
5.2 效能估算……………………………………………………………35
第六章結論與未來工作 ………………………………………………37
6.1 結論 ………………………………………………………………37
6.1 未來工作 …………………………………………………………37
參考文獻 ………………………………………………………………39
1. Jeffrey. C. Mogul, “TCP offload is a dumb idea whose time has come, ” Volume 9,
HOTOS''03: Proceedings of the 9th conference on Hot Topics in Operating Systems, May 2003,
Pages: 5-5.
2. Herman Chao. Eric Yeh, Venu Mannem, Joe Gervais, Bradley Booth, “Introduction to
TCP/IP Offload Engine(TOE),” 10 gigabit Ethernet alliance. version 1.0,2002.
3. Andy. Currid, “TCP Offload to the Rescue,” Volume 2, No.3, ACM Queue, May 1, 2004.
4. Julian Satran. Kalman Z. Meth, “Design of the iSCSI Protocol,” MSS ''03: Proceedings of
the 20th IEEE/11th NASA Goddard Conference on Mass Storage Systems and Technologies
(MSS''03), April 2003.
5. Srihari Makinen. Greg Regnier, Ramesh Illikkal, Ravi Iyer, Dave Minturn, Ram Huggahalli,
Don Newell, Linda Cline, Annie Foong,, “TCP Onloading for Data Center Servers,” vol. 37, IEEE
Computer Society Press, Nov 2004, pp. 48-55.
6. A.P.H. Foong, T.R. Hum, H.H. Patwardhan, J.R. Regnier, G.J., “TCP Performance Re-
Visited”, ISPASS ''03: Proceedings of the 2003 IEEE International Symposium on Performance
Analysis of Systems and Software, 2003, pp. 70-79.
7. W.R. Stevens ed., TCP/IP Illustrated, Volume 1: The Protocols, 1994.
8. C. Douglas ed., Computer Networks and Internets., 2001.
9. J.K.a.J. Pasquale, “Profiling and Reducing Processing Overheads in TCP/IP,” vol. 4, no. 6,
IEEE/ACM Transactions on Networking (TON), 1996, pp. 817 - 828.
10. I.E. Apostolos Dollas, Iosif Koidis, Ioannis Zisis, Christopher Kachris, “An Open TCP/IP
Core for Reconfigurable Logic. ”, Volume 00, FCCM ''05: Proceedings of the 13th Annual IEEE
Symposium on Field-Programmable Custom Computing Machines (FCCM''05), April 2005.
11. C.M. Kozierok, “The TCP/IP Guide: A Comprehensive, Illustrated Internet Protocols
Reference,” 2005, pp. 329-333.
12. IPBlaze. Corp, “IPBlaze TOE/NIC/PCIe products Spec,”
http://www.ipblaze.com/documents/PD009.pdf.
13. Seiko Epson. Corp, “Network Controllers S1S60000 document,” 2008;
http://www.epson.jp/device/semicon_e/product/network/s1s60000.htm.
14. Quadros. Inc., “RTXCnet Networking Protocol Suite,”
http://www.nohau.co.uk/products/rtxc/p_rtxc_net.htm.
15. Davicom Co, “DM9000A Fast Ethernet MAC Controller Datasheet,” 2005.
16. Davicom Co, “DM9000A APPLICATION NOTES,”, 2005.
17. “Access Control List,” http://en.wikipedia.org/wiki/Access_control_list.
18. 林灶生、劉紹漢, Verilog FPGA 晶片設計, 全華圖書, 2006.
19. Altera. Corporation, “Design Debugging Using the SignalTap II Embedded Logic
Analyzer.,” 2007.
20. Altera. Corporation, “DE2 Development and Education Board User Manual,”, 2006
21. Altera. Corporation., Mentor Graphics ModelSim Support3.
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