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研究生:陳世唐
研究生(外文):Shih-Tang Chen
論文名稱:化學合成金屬奈米晶粒於金氧半電容記憶體之應用
論文名稱(外文):Chemical synthesized metal nanoparticles for Metal-Oxide-Semiconductor capacitor memory applications
指導教授:呂正傑
指導教授(外文):Ching-Chich Leu
學位類別:碩士
校院名稱:國立高雄大學
系所名稱:化學工程及材料工程學系碩士班
學門:工程學門
學類:化學工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:134
中文關鍵詞:金奈米粒子白金奈米粒子氧化鉿高介電材料奈米晶粒記憶體
外文關鍵詞:Au NPsPt NPsHfO2High-k materialnanocrystal memory
相關次數:
  • 被引用被引用:1
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  • 收藏至我的研究室書目清單書目收藏:0
近年來,快閃記憶體利用浮動閘極、SONOS記憶體利用氮化物來儲存電荷等記憶體元件,常面臨尺寸微縮,而有漏電流等問題產生,為了解決這問題,因而發展出奈米晶粒記憶體。
本論文乃利用化學還原的方法製備出金與白金奈米粒子,並以自組裝方式將奈米粒子沈積在氧化層上,再覆蓋上氧化層材料以完成奈米晶粒記憶體電容結構並探討其記憶特性。論文中奈米晶粒記憶體電容結構可分為二大類,第一類使用傳統SiO2為穿隧氧化層,接著沈積金或白金奈米粒子,最後覆蓋以溶凝膠法(sol-gel法)合成鍍覆之高介電氧化鉿作為控制氧化層。第二類則是將奈米粒子沈積在溶凝膠法合成之氧化鉿穿隧氧化層上,再覆蓋上同樣利用溶凝膠法合成之氧化鉿以建構奈米晶粒記憶體電容結構。此外,論文中也探討於沈積奈米粒子後,以及鍍製完HfO2控制氧化層後,不同熱處理條件對記憶體特性的影響。
由實驗結果可知,使用白金奈米粒子作為奈米晶粒記憶體的補陷位置(Trapped center)可比金奈米粒子儲存較多的電荷,而利用溶凝膠法合成之高介電氧化鉿取代傳統SiO2作為穿隧及控制氧化層,則可得較佳的電荷儲存電性。依據本論文研究成果,選擇合適的記憶體結構搭配適當的熱處理條件,可獲得電荷儲存力及保存力均佳的奈米晶粒記憶體。
In recent years, the nonvolatile flash memory and SONOS memory devices, utilizing floating gate and silicon nitrides as charge storage nodes, had met the leakage and reliability challenges as the devices scaling down. In order to overcome these problems, the nanocrystal memory was proposed.
In this work, we used the chemical reduction method to synthesize the Au and Pt nanoparticles (NPs). Then the nanoparticles were self-assembled on top of the tunneling oxide layer and fully covered by the control oxide layer to the nanocrystal memory devices. Two kinds of nanocrystal memory devices were fabricated in present study. One is to deposit nanoparticles onto conventional SiO2 tunneling oxide and then it is covered by sol-gel synthesized HfO2 as a control oxide to construct a Si/SiO2/NPs/HfO2 memory structure. The other is to embed nanoparticles between both HfO2 tunneling oxide and control oxide. The heat treatment effects of nanoparticles and control oxide on the properties of nanocrystal memories were also discussed.
The results obtained from this work showed that the nanocrystal memory device utilizing Pt nanoparticles as trapped center could store much more electrons than Au nanoparticles. Moreover, the nanocrystal memories showed good retention characteristics when the conventional SiO2 tunneling oxide was replaced by high-k HfO2. According to our experimental results, the nanocrystal memory would achieve good charge storage performance and better retention characteristic by choosing a suitable memory structure and heat treatment parameter.
目錄
誌謝I
目錄III
表目錄VIII
圖目錄IX
中文摘要1
英文摘要2
第一章 緒論4
1.1 前言4
1.2 研究動機5
1.3 論文架構7
第二章 文獻回顧10
2.1半導體記憶體簡介10
2.1.1揮發性記憶體10
2.1.2非揮發性(Non-Volatile)記憶體11
2.2 記憶體操作簡介11
2.2.1寫入機制12
2.2.2抹除機制12
2.3記憶體性能考量12
2.4非揮性記憶體的發展13
2.5奈米晶粒記憶體的發展13
2.6金屬奈米粒子的發展歷史16
2.7金屬奈米粒子的製備17
2.8奈米粒子自組裝原理18
2.9記憶體中介電材料的選擇19
2.10旋鍍法(Spin coating method)20
2.11 MOS理論基礎21
2.11.1 MOS結構21
2.11.2理想MOS二極體C-V曲線22
2.11.3影響理想MOS二極體C-V特性的因素 23
2.11.4奈米晶粒記憶體中缺陷對C-V曲線的影響25
第三章 實驗方法45
3.1 實驗藥品45
3.2 實驗簡介46
3.3 奈米晶粒記憶體製備流程47
3.3.1 矽晶片表面清洗47
3.3.2 成長穿隧氧化層49
3.3.2.1 HfO2的製備與溶液條件49
3.3.2.2 鍍膜流程50
3.3.3氧化層表面清洗50
3.3.4氧化層表面處理51
3.3.5奈米粒子合成51
3.3.5.1 12nm金奈米粒子之製備51
3.3.5.2 3nm金奈米粒子之製備52
3.3.5.3 白金奈米粒子之製備52
3.3.6奈米粒子自組裝52
3.3.7控制氧化層53
3.4電極製備53
3.4.1頂電極製備53
3.4.2底電極製備53
3.5 實驗儀器54
3.5.1紫外光-可見光吸收光譜儀(UV-Vis Spectrometer)54
3.5.2奈米粒徑分析55
3.5.3掃描式電子顯微鏡(SEM)55
3.5.4 X光光電子能譜儀(ESCA)56
3.5.5橢圓偏光儀(Ellipsometer)分析57
3.5.6 X光繞射儀(XRD)57
3.5.7 原子力顯微鏡(AFM)58
3.5.8 電性量測59
3.5.8.1 電容-電壓量測(C-V量測)59
3.5.8.2 漏電流(I-V)量測59
3.5.8.3 電荷保存力量測(Retention)59
第四章 結果與討論65
4.1金奈米粒子合成65
4.1.1 12nm金奈米粒子之合成65
4.1.2 3nm金奈米粒子之合成66
4.1.3 白金奈米粒子之合成66
4.2 金屬奈米粒子之自組裝67
4.2.1 APTMS濃度對金奈米粒子覆蓋密度的影響67
4.2.2自組裝於基板上之奈米粒子分析68
4.3奈米晶粒記憶體特性分析69
4.3.1 Si/SiO2/3nm Au/HfO2結構的奈米晶粒記憶體 69
4.3.1.1 C-V曲線的記憶效應(Memory effect)69
4.3.1.2閘極電壓對VFB的影響72
4.3.1.3電荷保存力(Retention)特性分析 73
4.3.2 Si/SiO2/5nm Pt/HfO2結構的奈米晶粒記憶體 73
4.3.2.1 C-V曲線的記憶效應(Memory effect)73
4.3.2.2閘極電壓對VFB的影響74
4.3.3 HfO2為穿隧氧化層及控制氧化層的金奈米晶粒記憶體74
4.3.3.1 HfO2結晶特性分析74
4.3.3.2 HfO2表面形貌分析75
4.3.3.3 HfO2表面的金奈米粒子分佈75
4.3.3.4 C-V曲線的記憶效應(Memory effect)75
4.3.3.5閘極電壓對VFB的影響77
4.3.3.6電荷保存力(Retention)特性分析77
4.3.4 HfO2為穿隧氧化層及控制氧化層的白金奈米晶粒記憶體78
4.3.4.1 C-V曲線的記憶效應(Memory effect)78
4.3.4.2閘極電壓對VFB的影響79
第五章 結論109
第六章 參考文獻110

表目錄
表2.1奈米晶粒記憶體的發展歷史表27
表4.1 12nm金奈米粒子覆蓋密度隨不同濃度APTMS的變化80
表4.2 3nm金奈米粒子覆蓋密度隨不同濃度APTMS的變化80
表4.3不同控制氧化層電荷密度的比較80
表4.4以SiO2為穿隧氧化層的金與白金奈米記憶體電性比較81
表4.5以不同厚度的HfO2為穿隧氧化層的金與白金奈米記憶體電性比較81

圖目錄
圖1.1快閃記憶體優點8
圖1.2浮動閘極記憶體9
圖1.3奈米晶粒記憶體9
圖2.1 DRAM的等效電路圖28
圖2.2六個電晶體組成的SRAM記憶胞結構圖28
圖2.3記憶體的寫入操作29
圖2.4記憶體的抹除操作29
圖2.5 SONOS記憶體30
圖2.6析出法沈積鍺奈米晶粒30
圖2.7金屬膜厚度對奈米粒子形成的影響31
圖2.8奈米晶粒記憶體的能帶圖及電荷儲存效應(a)半導體奈米粒子、(b)金屬奈米粒子32
圖2.9高介電材料HfO2取代SiO2氧化層的電性比較33
圖2.10 (a) 利用化學還原法合成金晶粒的TEM與UV-Vis圖34
圖2.10 (b) 金(Au)奈米晶粒記憶體C-V曲線圖34
圖2.11鉑(Pt)奈米晶粒記憶體C-V曲線圖35
圖2.12金(Au)奈米晶粒記憶體C-V曲線圖35
圖2.13 (a) 鉑(Pt)奈米晶粒記憶效應36
圖2.13 (b) 鉑(Pt)奈米晶粒電荷保存時間36
圖2.14不同功函數金屬粒子的能帶圖(a)鉑、(b)金、(c)鎳、(d)鎢37
圖2.15金屬奈米粒子的製備38
圖2.16奈米粒子自組裝方法39
圖2.17旋鍍示意圖39
圖2.18 MIS結構示意圖40
圖2.19理想MOS二極體的 (a) 能帶圖,(b)電荷分佈圖40
圖2.20 MOS二極體在聚集區情況下的(a) 能帶圖,(b)電荷分佈圖41
圖2.21 MOS二極體在空乏區情況下的 (a) 能帶圖,(b)電荷分佈圖41
圖2.22 MOS二極體在反轉區情況下的 (a) 能帶圖,(b)電荷分佈圖41
圖2.23在MOS結構中各種缺陷的分佈位置圖42
圖2.24介面陷阱電荷對電容電壓特性曲線的影響42
圖2.25固定氧化層電荷量對平帶電壓的影響43
圖2.26可移動金屬離子造成C-V曲線的效應43
圖2.27奈米晶粒缺陷造成C-V曲線的效應44
圖3.1以SiO2為穿隧氧化層的奈米晶粒記憶結構60
圖3.2以HfO2為穿隧氧化層的奈米晶粒記憶結構60
圖3.3 HfO2溶液製備流程61
圖3.4烘烤(Baking)流程61
圖3.5 奈米粒子自組裝流程圖62
圖3.6 上電極形狀圖(Shadow mask pattern)63
圖3.7 奈米晶記憶體電容製備流程圖-64
圖4.1 (a) 12nm金奈米粒子溶液的可見、紫外光光譜儀圖(UV-Visible Spectrophotometer)及溶液照片82
圖4.1 (b) 12nm金奈米粒子的奈米粒徑分析83
圖4.1 (c) 12nm金奈米粒子的SEM圖83
圖4.2 (a) 3nm 金奈米粒子溶液的可見、紫外光光譜儀圖(UV-Visible Spectrophotometer)及溶液照片84
圖4.2 (b) 3nm金奈米粒子的奈米粒徑分析85
圖4.2 (c) 3nm金奈米粒子的SEM圖85
圖4.3 (a) 白金奈米粒子的奈米粒徑分析86
圖4.3 (b) 白金奈米粒子的SEM圖86
圖4.4 12nm金奈米粒子在(a)1mM、(b)5mM、(c)10mM、(d)20mM、(e)55mM APTMS濃度下SEM圖87
圖4.5 3nm金奈米粒子在(a)1mM、(b)5mM、(c)10mM、(d)20mM、(e)55mM APTMS濃度下的SEM圖88
圖4.6 12nm金奈米粒子覆蓋密度隨不同濃度APTMS的變化89
圖4.7 3nm金奈米粒子覆蓋密度隨不同濃度APTMS的變化89
圖4.8金奈米粒子的能量散射光譜儀(EDS)圖90
圖4.9 (a)12nm與(b)3nm金奈米粒子的X光繞射(XRD)圖90
圖4.10 (a) 無嵌鑲3nm金(Au)奈米粒子的C-V曲線,(b) 嵌鑲3nm金(Au)奈米粒子的C-V曲線91
圖4.11 3nm金奈米粒子於氧氣氛下,(a)無熱處理、(b) 200℃、(c) 300℃、(d) 400℃、(e) 500℃熱處理一小時的SEM圖92
圖4.12 3nm金奈米粒子於氧氣氛下,不同溫度熱處理1小時的(a)粒徑變化、(b)覆蓋密度變化93
圖4.13 嵌鑲3nm金(Au)奈米晶粒隨不同熱處理條件的C-V曲線94
圖4.14奈米晶粒記憶體中,3nm金奈米粒子於(a)200℃、(b)300℃氧氣熱處理1小時,,控制氧化層HfO2通氧氣熱處理500℃,10分鐘的C-V曲線95
圖4.15奈米晶粒記憶體中,3nm金奈米粒子通氧氣於(a)200℃、(b)300℃溫度下熱處理1小時,,控制氧化層HfO2通氧氣熱處理500℃,10分鐘的平帶電壓對閘極電壓變化96
圖4.16奈米晶粒記憶體的電荷保存特性,其中3nm金奈米粒子經氧氣200℃熱處理1小時,控制氧化層HfO2經氧氣500℃,十分鐘熱處理97
圖4.17 白金奈米粒子(a)不經熱處理、(b)氧氣300℃熱處理1小時的奈米晶粒記憶體C-V曲線97
圖4.18白金奈米粒子(a)不經熱處理、(b)氧氣300℃熱處理1小時的奈米晶粒記憶體平帶電壓對閘極電壓變化98
圖4.19 8.2nm HfO2經爐管退火900℃,1分鐘之XRD圖99
圖4.20 10.4nm HfO2經爐管退火900℃,1分鐘之XRD圖99
圖4.21厚度(a)8.2nm、(b)10.4nm HfO2薄膜表面形貌AFM圖100
圖4.22自組裝於厚度(a)8.2nm、(b)10.4nm HfO2薄膜上的3nm金奈米粒子SEM圖101
圖4.23以厚度(a)8.2nm、(b)10.4nm HfO2作為穿隧氧化層的金奈米晶粒記憶體C-V曲線102
圖4.24 (a)8.2nm HfO2與(b)10.4nm HfO2穿隧氧化層上的金奈米粒子經200℃與300℃氧氣熱處理1小時的奈米晶粒記憶體C-V曲線103
圖4.25厚度(a)8.2nm、(b)10.4nm HfO2穿隧氧化層上金奈米晶粒經氧氣200℃熱處理1小時,控制氧化層HfO2通氧氣熱處理500℃,10分鐘的奈米晶粒記憶體C-V曲線104
圖4.26厚度(a)8.2nm HfO2、(b)10.4nm HfO2作為穿隧氧化層的金奈米晶粒記憶體平帶電壓對閘極電壓變化圖105
圖4.27 10.4 nm HfO2穿隧氧化層上的金奈米粒子經氧氣200℃熱處理1小時的奈米晶粒記憶體平帶電壓對閘極電壓變化圖106
圖4.28 10.4 nm HfO2穿隧氧化層上的金奈米粒子經氧氣200℃熱處理1小時的奈米晶粒記憶體電荷保存特性106
圖4.29 8.2 nm HfO2作為穿隧氧化層的白金奈米晶粒記憶體C-V曲線圖107
圖4.30 10.4 nm HfO2作為穿隧氧化層的白金奈米晶粒記憶體C-V曲線圖107
圖4.31 8.2 nm HfO2作為穿隧氧化層的白金奈米晶粒記憶體平帶電壓對閘極電壓變化圖108
圖4.32 10.4 nm HfO2作為穿隧氧化層的白金奈米晶粒記憶體平帶電壓對閘極電壓變化圖108
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