臺灣博碩士論文加值系統

本論文針對WiMAX通訊系統規格設計了二顆CMOS低雜訊放大器，第一顆為應用於2-6GHz之寬頻低雜訊放大器，第二顆為2.4GHz及5.2GHz雙頻低雜訊放大器，均使用台灣積體電路製造公司(TSMC)0.18μm CMOS 製程設計完成。以上晶片均透過國家系統晶片設計中心(Chip Implementation Center, CIC)下線製造。亦透過台南CIC高頻量測系統量測完成。
本論文所設計的放大器晶片，對於第一顆所設計的放大器是部分工作的，在1.2V工作電壓下，有11.5mA的電流，功率消耗為13.8mW，量測的數據與模擬的數據有所差距的主要原因為VDD線段的損耗使得MOS偏壓點產生偏差以及電路中的訊號線旁置入dummy使得訊號線與接地端產生下地電容，使頻率偏移。；而第二顆放大器因金屬線段之間產生寄生電容使得電路mismatch，其量測特性與模擬差異甚大，因此應將較為敏感的訊號金屬線段進行電磁模擬工作以及在電路佈局中加入旁路電容以濾除直流金屬線上多餘的交流雜訊便可得到改善。

In this thesis, I had designed two chips to meet WiMAX communication system standards, The first one is applicable on 2-6 GHz wideband low noise amplifier; the second is useful for 2.4GHz and 5.2GHz dual-band low noise amplifier. The low noise amplifiers were fabricated using TSMC 0.18μm CMOS manufacturing process, the measurement was done by RF measurement lab in Chip Implementation Center (CIC)..
The first chip is partial working on 1.2V, with 11.5mA current and 13.8mW power consumption, measurement and simulation data cannot fitting well. The major issue is caused by (1) the loss of metal line influence the bias voltage of MOS, and (2) the ground dummy which placed near the signal path will cause a parasitic capacitor to ground which will cause frequency shifting. Because of the parasitic capacitor which caused circuit mismatch between metal line of signal path, the second cannot meet the simulated data, Thus, it should simulate EM(electric magnetic) with metal line of signal path which is sensitive and used bypass capacitor to filter the noise on the dc metal line that could be improved.

中文摘要………………………………………………………………………...i
英文摘要………………………………………………………………………..ii
誌謝……………………………………...……………………………………..iii
目錄……………………………………...……………………………………..iv
表目錄…………………………………...……………………………………..vi
圖目錄…………………………………...…………………………………….vii
第一章
序論………………………………………………………………...1
1.1 研究動機..………………………...…………………….………………...1
1.2 論文架構..………………………...…………………….………….……..5
第二章
低雜訊放大器(LNA)規格設計……………………………………6
2.1 散射參數..………………………...…………………….………….……..6
2.2 功率增益及穩定度..……………...…………………….………….……..7
2.3 CMOS雜訊..……………………...…………………….………….…....10
2.3.1 通道熱雜訊……………………………………..…..…………..10
2.3.2 閃爍雜訊………………………………………..…..…………..11
2.3.3 電晶體的雜訊……………………………………....…………..12
2.4 雜訊指數的定義..………………...…………………….………….…....13
2.5 串接雜訊指數…..………………...…………………….………….…....14
2.6 線性度…………..………………...…………………….………….…....15
2.6.1功率1dB壓縮點..…...…………………..……….………….…....17
2.6.2輸入三階截斷點..…...…………………….……………..….…....18
2.7 電路設計流程…..………………...…………………….………….…....20
iv
第三章
電路佈局技巧……………………………………………………..21
3.1 元件的置放與走線..……………...…………………….………….…....21
3.2 走線的寬度………..……………...…………………….………….…....22
3.3 走線的長度………..……………...…………………….………….…....23
3.4 走線的連線………..……………...…………………….………….…....24
3.5 走線的轉角………..……………...…………………….………….…....25
3.6 走線與元件的連接..……………...…………………….………….…....27
3.7 走線切勿形成迴路..……………...…………………….………….…....28
3.8 佈局中電感的擺放..……………...…………………….………….…....29
3.9 佈局中dummy的擺放..……………...…..…………….………….…....31
3.10 佈局中直流與訊號走線的擺放..……………...…………….…….…....33
第四
章 2~6GHz LC-ladder 寬頻低雜訊放大器...………………………..34
4.1 輸入放大器的選擇與匹配..……………...…………………...….…….34
4.2 LC-ladder 寬頻低雜訊放大器……...…...…………………...….…….40
4.3 電路模擬結果………………………...…...…………………...….…….44
4.4 晶片量測與討論…………………...…...…………………...….…….…40
第五章
2.4GHz &5.2GHz雙頻低雜訊放大器…..………………………..62
5.1 雙頻低雜訊放大器的選擇..……………...…………………...….…….62
5.2 電感電容開關雙頻低雜訊放大器……...…………………...….…….65
5.3 電路模擬結果……...……………………………………...….…….…...70
5.4 晶片量測與討論…...……………………………………...….…….…...78
第六章
結論與未來工作……………………..…..………………………..89
參考文獻……………………………………………..………………………..92

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