跳到主要內容

臺灣博碩士論文加值系統

(34.204.180.223) 您好!臺灣時間:2021/08/05 16:37
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:鄒昌廷
研究生(外文):Chang-Ting Tsou
論文名稱:可擴充式模組化數位比較器設計
論文名稱(外文):Design of an Expandable and Module-Based Digital Comparator
指導教授:劉偉行劉偉行引用關係
學位類別:碩士
校院名稱:國立虎尾科技大學
系所名稱:光電與材料科技研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:55
中文關鍵詞:數位比較器模組化可擴充式
外文關鍵詞:digital comparatormodule-basedexpandable
相關次數:
  • 被引用被引用:0
  • 點閱點閱:350
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在本論文中提出數種全新的CMOS設計之可擴充數位比較器。所提出的數位比較器適用於兩個8位元二進位數字之比較,可比較出大於、等於以及小於的關係。

第一個比較器為使用新型二位元數位比較器加上擴充模組實現的8位元數位比較器;第二個比較器為使用新型一位元數位比較器電路加上相關輸入端的邏輯判斷電路所組合而成;第三個比較器亦為使用新型一位元數位比較器電路實現,但是與第二個比較器不同之處是輸入端並沒有使用的邏輯判斷電路;最後一個比較器為使用新型一位元數位比較器外加上開關去實現,與第三個比較器不同之處是在輸出端部分增加了一組開關,此一設計之用意是避免電路在切換時所出現的高阻抗狀態,以確保電路的正確性。

本論文所提出之數位比較器經由HSpice軟體模擬,模擬結果顯示,當供應電壓為3.3V時,電路可在操作頻率100MHz下正常工作。相關電路進一步使用TSMC N-Well 0.35微米2P4M製程下線製作;晶片量測結果可證明設計構想之正確性。
Several new CMOS module-based expandable digital comparators have been developed in the thesis. The proposed digital comparators can be used to perform the comparison between two multiple – bit binary numbers, and decide which one is equal, greater or less than the other one.

The first proposed comparator was implemented by using new 2-bit comparators and related expanding modules. The second proposed comparator was composed of 1-bit comparators and with some necessary deciding logic circuits on their inputs. The third proposed comparator also uses 1-bit comparators as core circuits; however unlike the second proposed one, there are no deciding logic circuits on their inputs. The last proposed comparator was realized by using 1-bit comparators and some switches. The difference between the third and the last comparator is the switch used at the output of the last proposed comparator. The switch is used to eliminate the high impedance state probably occurred during the transition, consequently correct outputs can be given.

All the proposed circuits have been simulated with the HSpice. As the supply voltage is 3.3V, simulation results show that the related circuits are functional with 100MHz input signal. The proposed comparators are further fabricated by using TSMC 0.35?m mixed-signal 2P4M polycide 3.3/5V process. Measurement results are consistent with the design methodology.
摘 要................................................. i
Abstract.............................................. ii
誌 謝................................................. iii
表目錄................................................ v
圖目錄................................................ vi
符號說明.............................................. viii
第一章 前言........................................... 1
1.1 研究動機與目的.................................... 1
1.2 文獻回顧.......................................... 1
1.3 研究重點.......................................... 2
1.4 論文架構.......................................... 2
第二章 數位比較器簡介................................. 4
2.1 傳統式數位比較器.................................. 4
2.2 可擴充式數位比較器................................ 7
第三章 新型數位比較器設計............................. 13
3.1 使用二位元數位比較器所實現之八位元數位比較器...... 13
3.2 新型一位元數位比較器與相關輸入端邏輯電路實現八位元數位比較器.................................................. 16
3.3 使用模組化一位元數位比較器實現八位元數位比較器.... 21
3.4 模組化一位元數位比較器與開關實現八位元數位比較器.. 25
第四章 晶片設計與量測................................. 34
4.1 設計流程.......................................... 34
4.2 晶片佈局與Post-Layout Simulation.................. 35
4.3 量測考量.......................................... 44
4.4 量測結果.......................................... 44
第五章 結論........................................... 48
參考文獻.............................................. 49
附錄.................................................. 51
英文論文大綱.......................................... 52
簡歷.................................................. 55
[1] Peter, K.K.L.; Tan, E.C.; “Digital comparator for non- algorithmic routing,” Proceedings of the 2003 Joint
Conference of the Fourth International Conference on
Information, Communications and Signal Processing,
Vol. 3, pp. 1949 – 1951, Dec. 2003.
[2] Cheng Shun-Wen, “A HIGH-SPEED MAGNITUDE COMPARATOR
WITH SMALL TRANSISTOR COUNT,” Proceedings of the 2003
10th IEEE International Conference on Electronics,
Circuits and Systems, Vol.3, pp.1168-1171 Dec. 2003.
[3] NICK A. FARMER; “A Digital Comparator for Use with
Computer Displays,” Proceedings of the IEEE
Transactions on Computers, Vol. C-18, pp.269-270 Mar.
1969.
[4] Nandhasri, K.; Ngarmnil, J., “Designs of analog and
digital comparators with FGMOS,” Proceeding of the
2001 IEEE International Symposium on Circuits and
Systems, Vol. 1, pp. 25 – 28, May 2001.
[5] 鄒昌廷、劉偉行,“利用傳輸閘實現可擴充式8位元數位比較
器”,2007 National Computer Symposium, Vol. 2,
pp.478-487, Dec 2007,台中。
[6] 劉偉行、鄒昌廷、王晟瑋、曾世緯、蕭閎隆、陸貴葉,
“Realization of A Expandable 8-bit Digital Comparator
Using 2-bit Digital comparator”,2008 PAL 系統雛型與電
路設計創新應用研討會, pp. 306-310, Otc. 2008,台中。
[7] 劉偉行、鄒昌廷,“新型數位比較器設計”, Proceedings of
the Fourth Intelligent Living Technology Conference
(2009), pp. 699-703, Jun. 2009,台中。
[8] 劉偉行,鄒昌廷,王晟瑋,“一種改良式可擴充之8 位元數位比
較器設計,”2008 電子工程技術研討會, 97 年6 月19 日,高
雄。
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top