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研究生:李明彥
研究生(外文):Ming-Yen Li
論文名稱:酒精催化化學氣相沈積奈米碳管網薄膜電晶體研製
論文名稱(外文):Study of Carbon Nanotube Network Field-Effect Transistors Synthesized by Alcohol Catalytic Chemical-Vapor-Deposition
指導教授:鄭錦隆
指導教授(外文):Chin-Lung Cheng
學位類別:碩士
校院名稱:國立虎尾科技大學
系所名稱:材料科學與綠色能源工程研究所
學門:工程學門
學類:綜合工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:77
中文關鍵詞:奈米碳管網薄膜電晶體高介電常數材料移動率
外文關鍵詞:Carbon nanotube network (CNTN)thin-film transistorhigh-K materialmobility
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本篇論文藉由酒精催化化學(ACCVD)氣相沉積成長奈米碳管網,並使用鈷/鉬雙金屬當催化劑塗佈於SiO2/Si(100)堆疊基板,並以酒精作為碳源,搭配各種成長時間及溫度成長奈米碳管網場效電晶體。其中使用HfO2當電晶體的閘介電材料層。藉由電性量測分析此元件的各種特性如汲極電流-汲極電壓、汲極電流-閘極電壓、移動率、次臨界擺幅及最大電導。研究結果得知由ACCVD成長奈米碳管網薄膜電晶體具有雙極特性。藉由調整電晶體的尺寸可獲得On/Off ratio到達8 order,最大移動率 1×105 cm2/Vs,最小次臨界擺幅(subthreshold swing) 3.83 mV/decade,及最大電導(transconductance) 1.93 (S)。
Abstract
In this thesis, the synthesizing high-quality carbon nanotube network field-effect transistor (CNTNFET) has been developed directly by means of the low-temperature catalytic CVD method using ethanol (ACCVD). A metal acetate solution was prepared by dissolving molybdenum acetate and cobalt acetate into ethanol. By modulated the various growth temperatures and time, the high-quality CNTN can be achieved. The CNTNFETs with HfO2 as gate dielectrics were achieved. Various electrical properties including drain current-drain voltage (Id-Vd), drain current-gate voltage (Id-Vg), mobility, subthreshold swing, and transconductance were obtained using current-voltage instrument. Research results show that the bipolar property of the CNTNFET synthesized by alcohol catalytic chemical-vapor-deposition can be demonstrated. The electrical properties of the CNTNFET with an on-off current ratio of 8, a hole mobility of 1×105 cm2/Vs, a subthreshold swing of 3.83 mv/decade, a transconductance of 1.93 (A/V) were demonstrated.
目 錄
摘要…………………………………………………………………………….i
Abstract.…………………………………………………………….…………..ii
誌謝………………………………………………………………………….…iii
目錄……………………………………………………………………...……..iv
圖目錄………………………………………………………………………….vi
第一章 序論……………………………………………………………………. 1
1.1 奈米碳管薄膜電晶體之發展概述………………………...................... 1
1.2 高介電材料二氧化鉿(HfO2)作為閘極介電層之理由……………….. 2
1.3 研究動機…………………………………………………………..........3
1.4 論文架構………………………..………....................................………4
第二章 元件製程與量測………………………………………………………. 5
2.1酒精催化化學氣相沉積奈米碳管網薄膜電晶體製程………………... 5
2.2元件製程………………………………………………………………. 5
2.2.1 晶圓準備………………………………………………………. 5
2.2.2 Si/SiO2表面改質製程…………………………………….……. 6
2.2.3 Dip-Coating製程……………………….……………………….6
2.2.4成長奈米碳管網………………………………………….…… .7
2.2.5蝕刻奈米碳管網做為電晶體之通道…………...……………... 7
2.2.6源極/汲極電極製程……………………………………...……. 8
2.2.7蒸鍍介電層…………………………………………………….. 9
2.2.8閘極電極製程………………………………………………….. 9
2.2.9蝕刻氧化鉿做為Contact hole…………………………………10
2.3電性量測參數……………………………………………….………… 10
2.3.1汲極電流-汲極電壓量測…………………………..………… 11
2.3.2汲極電流-閘極電壓量測…………………………….………. 11
2.3.3移動率量測…………………………………………………… 11
2.3.4次臨界擺幅量測……………………………………………….12
2.3.5最大電導量測……………………………………………….....12
2.4材料物性量測……………………………………………..……………12
2.4.1場發掃描式電子顯微鏡(Field Effect - Scanning Electron Microscope)………………………………………………….12
2.4.2穿透式電子顯微鏡(Transmission electron microscopy, TEM)………………………………………………………….13
2.4.3 薄膜測厚儀 (n&k analyzer)…………………...……………..13
2.4.4 拉曼光譜分析儀 (Raman Spectrometer)………...….……….13
2.4.5霍爾效應量測…………………..…….………………………..14
第三章 不同通道長度及磷板摻雜製程技術對酒精催化化學氣相沈積奈米碳管網薄膜電晶體之研究………................................................... 19
3.1 研究動機……………………………………………………………… 19
3.2 結果與討論…………………………………………………………… 19
3.2.1不同通道長度對奈米碳管網薄膜電晶體特性之結果與討論…………………………....................................................... 19
3.2.2 磷板摻雜製程技術對奈米碳管網薄膜電晶體之結果與討論……………………………………………………………... 24
第四章 結論與建議…………………………………………………...……… 68
4.1結論…………………………………………………………...……….. 68
4.2 建議……………………………………………………………..…….. 68
參考文獻……………………………………………………………..………... 70
作者簡歷…………………………………………………………..…………... 73
英文大綱…………………………………………………………..……...........74
[1]. R. Martel, T. Schmidt, H. R. Shea, T. Hertel, and Ph. Avouris, “Single- and multi-wall carbon nanotube field-effect transistors”, Appl. Phys. Lett. 73, 2447 (1998)
[2]. L. A. W. Robinson,et al., “Fabrication of self-aligned side gates to carbon nanotubes”, NANOTECHNOLOGY 14, pp. 290-293, 2003
[3]. S. J. Wind et al., “Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes,” Appl. Phys. Lett. 80, 3817 (2002)
[4]. E. S. Snow, J. P. Novak, P. M. Campbell, and D. Park, “Random networks of carbon nanotubes as an electronic material”, Appl. Phys. Lett. 82, 2145 (2003)
[5]. X. Duan, C. Niu, V. Sahi, J. Chen, J. W. Parce, S. Empedocles, and J. L. Goldman, “High-performance thin-film transistors using semiconductor nanowires and nanoribbons,” Nature, vol.425, pp.274, 2003.
[6]. Wei Xue, Yi Liu, and Tianhong Cui, “High-mobility transistors based on nanoassembled carbon nanotube semiconducting layer and SiO2 nanoparticle dielectric layer.”, Appl. Phys. Lett., Vol. 89, 163512,2006
[7]. Hyunhyub Ko and Vladimir V. Tsukruk “Liquid-Crystalline Processing of Highly Oriented Carbon Nanotube Arrays for Thin-Film Transistors. ” Nano Letters vol.6, No7 1443-1448, 2006
[8]. Nobuhito Inami, Mohd Ambri Mohamed, Eiji Shikoh, and Akihiko Fujiwara “Device characteristics of carbon nanotube transistor fabricated by direct growth method. ” APPLIED PHYSICS LETTERS 92, 243115 ,2008.
[9]. J. Vaillancourt, X. Lu, X. Han and D.C. Janzen. “High-speed thin-film transistor on flexible substrate fabricated at room temperature. ”, ELECTRONICS LETTERS, Vol. 42 No. 23,1365-1366, November 2006
[10]. Axel Schindler et al., “Solution-deposited carbon nanotube layers for flexible display applications. ” Physica E 37 (2007) 119–123
[11]. Eun Ju Bae, Yo-Sep Min, Un Jeong Kim, and Wanjun Park. “Random network transistors of carbon nanotubes directly grown on glass substrate. ” Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE Vol 1, 482-483, 2006
[12]. Xuliang Han, Daniel C. Janzen, Jarrod Vaillancourt, and Xuejun Lu. “ A Flexible Thin-Film Transistor with High Field-Effect Mobility by Using Carbon Nanotubes.” Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE Vol 1, 296-297, 2006.
[13]. E. Rosenbaum, and L. F. Register, IEEE Transactions on Electron Devices, “Mechanism of Stress-Induced Leakage Current in MOS Capacitors. ” Vol. 44, 317-323, No. 2, February (1997).
[14]. F. Irrera, and B. Riccò, “SILC Dynamics in MOS Structures Subject to Periodic Stress. ” IEEE Transactions on Electron Devices, Vol. 49, No. 10, 1729- 1735 ,October (2002).
[15]. Y. Taur, “The incredible shrinking transistor. ”, IEEE Spectrum 7, vol 36, 25 - 29 , July 1999
[16]. Y. C. Yeo, T. J. King and Chenming Hu, “MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations”, Trans. Electron Devices 50, 1027 (2003)
[17]. J. Kwo, M. Hong, A. R. Kortan, K. T. Queeney, Y. J. Chabal, J. P. Mannaerts, T. Boone, J. J. Krajewski, A. M. Sergent and J. M. Rosamilia, “High ε gate dielectrics Gd2O3 and Y2O3 for silicon”, Appl. Phys. Lett. 77, 130 (2000)
[18]. G. D. Wilk, R. M. Wallace and J. M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations”, J. Appl. Phys. 89, 5243 (2001)
[19]. M. Hong, J. Kwo, A. R. Kortan, J. P. Mannaerts and A. M. Sergent, “Epitaxial Cubic Gadolinium Oxide as a Dielectric for Gallium Arsenide Passivation”, Science 283, 1897 (1999)
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