臺灣博碩士論文加值系統

隨著影像處理與通訊系統的快速發展，高解析度的類比數位轉換器常被應用在這些前端接收路徑之中，另一方面近年來個人可攜式電子產品的成長，對於類比數位轉換器的功率消耗需求越來越嚴苛，所以在解析度和功率消耗的考量下，眾多種類的高速類比數位轉換器架構當中，管線式類比數位轉換器是一個很好的選擇。管線式類比數位轉換器擁有速度快、解析度高及功率消耗低的優點，因此能達到高速的輸入性能和快速的處理能力。在本論文中，將針對管線式類比數位轉換器做設計，並在前端取樣保持電路的設計上使用米勒電容效應的方法，此技術在取樣模式與保持模式下提供兩種不同的等效電容值，使得電路的取樣速度與精確度皆可以得到改善。
在論文中，使用TSMC 0.35um 2P4M的製程，實現一個電源電壓為1.5V，取樣頻率為20MHz的十位元管線式類比數位轉換器，根據佈局後模擬結果，輸入電壓範圍為±0.5V，整體電路工作於371.09375KHz的輸入訊號頻率下可得到SNDR為52dB，功率消耗約為32mW，電路佈局面積為2276×2072um2。

With the fast growth of video process and communication systems, high-resolution analog-to-digital converters (ADCs) are required in the front-end received path. In recent years, the growth of portable consumer electronics, power dissipation is becoming an increasingly important design issue in analog-to-digital converters. In many types of high-speed analog-to-digital converter (ADC) architectures, a pipelined ADC architecture has become an attractive choice. Pipelined ADC has the advantages of high-speed, high-resolution and low power dissipation, and therefore it can achieve good dynamic range performances and fast throughput. This thesis focuses on designing the pipelined ADC. Furthermore, Miller-capacitance effect method is used to the front-end sample-and-hold (S/H) circuit. It has two different capacitance values at the sampling phase and hold phase. Miller-capacitance-based S/H circuit can be employed to relax the requirements for the first pipeline stage.
In this thesis, a 10-bits 20MHz pipelined ADC implemented using the TSMC 0.35um CMOS process with a 1.5V power supply. In the result of post-simulation, this design achives a signal-to-noise and distortion ratio (SNDR) of 52dB at an input signal frequency of 371.09375KHz and an input range of ±0.5V that estimated power dissipation is about 32mW. The layout area is about 2276×2072um2.

中文摘要…………………………………………………………………… i
英文摘要…………………………………………………………………… ii
誌謝………………………………………………………………………… iii
目錄………………………………………………………………………… iv
表目錄……………………………………………………………………… vii
圖目錄……………………………………………………………………… xi
第一章 緒論……………………………………………………………… 1
1.1 研究動機…………………………………………………………… 1
1.2 類比數位轉換器的簡介…………………………………………… 2
1.2.1 奈奎氏類比數位轉換器 (Nyquist rate ADC) ………………… 2
1.2.2 超取樣類比數位轉換器 (Oversampling ADC) ……………… 4
1.3 論文架構…………………………………………………………… 4
第二章 高速類比數位轉換器之基本概念……………………………… 6
2.1 簡介………………………………………………………………… 6
2.2 高速類比數位轉換器的架構介紹………………………………… 6
2.2.1 快閃式類比數位轉換器 (Flash ADC)………………………… 6
2.2.2 二階式類比數位轉換器 (Two-Step ADC) …………………… 8
2.2.3 管線式類比數位轉換器 (Pipelined ADC) …………………… 9
2.2.4 分時平行式類比數位轉換器 (Time-Interleaved ADC) ……… 10
2.3 管線式類比數位轉換器電路動作分析…………………………… 12
2.4 類比數位轉換器的特性參數……………………………………… 15
2.4.1 最小步階電壓 (LSB)…………………………………………… 15
2.4.2 取樣頻率 (Sampling Rate)……………………………………… 15
2.4.3 解析度 (Resolution) …………………………………………… 16
2.4.4 功率消耗 (Power Dissipation) ………………………………… 16
2.4.5 輸入範圍 (Input Range)………………………………………… 16
2.4.6 輸入頻寬 (Input Bandwidth)…………………………………… 16
2.4.7 抵補電壓 (Offset Voltage)……………………………………… 17
2.4.8 增益誤差 (Gain Error) ………………………………………… 17
2.4.9 差值非線性 (Differential Non-Linearity, DNL) ……………… 18
2.4.10 積分非線性 (Integral Non-Linearity, INL)…………………… 18
2.4.11 單調性 (Monotonicity)………………………………………… 19
2.4.12 遺失碼 (Missing Code) ……………………………………… 19
2.4.13 全諧波失真 (Total Harmonic Distortion, THD)……………… 20
2.4.14 訊號對雜訊比 (Signal-to-Noise Ratio, SNR)………………… 20
2.4.15 訊號對雜訊及失真比 (Signal-to-Noise and Distortion Ratio,
SNDR)………………………………………………………… 21
2.4.16 無寄生訊號動態範圍 (Spurious-Free Dynamic Range,
SFDR)………………………………………………………… 21
2.4.17 有效位元數 (Effective Number of Bits, ENOB)……………… 22
2.5 MOS開關於電路設計時考量之因素……………………………… 22
2.5.1 電荷注入效應 (Charge Injection)……………………………… 22
2.5.1.1 仿造元件 (Dummy Device)………………………………… 23
2.5.1.2 互補式MOS開關…………………………………………… 24
2.5.1.3 全差動式MOS電路………………………………………… 25
2.5.2 時脈饋入效應 (Clock Feed-Through) ………………………… 26
2.5.3 低電源電壓設計時MOS開關的導通電阻 …………………… 27
2.5.4 MOS開關導通電阻在低電源電壓設計之改善方法 ………… 29
2.5.4.1 時脈提升 (Clock Booster)………………………………… 29
2.5.4.2 開關運算放大器 (Switched-Opamp)…………………… 30
2.5.4.3 拔靴帶式開關 (Bootstrapped Switch)…………………… 30
2.5.4.4 臨界電壓比例 (VT Scaling) ……………………………… 31
2.6 數位錯誤校正技術(Digital Error Correction Technique) ………… 32
第三章 管線式類比數位轉換器之行為模擬…………………………… 38
3.1 簡介………………………………………………………………… 38
3.2 Matlab/Simulink中使用的基本方塊函數………………………… 38
3.3 管線式類比數位轉換器的行為模型 (Behavior Model of
Pipelined ADC) …………………………………………………… 45
3.3.1 取樣保持電路 (Sample and Hold Circuit) …………………… 45
3.3.2 1.5位元次類比數位轉換器 (1.5-bit Sub_ADC)……………… 46
3.3.3 乘法式數位類比轉換器 (MDAC) …………………………… 47
3.3.4 兩位元快閃式類比數位轉換器 (2-bit Flash_ADC)…………… 48
3.3.5 全加器 (Full Adder) …………………………………………… 50
3.3.6 數位錯誤校正電路……………………………………………… 51
3.3.7 十位元管線式類比數位轉換器 (10-bit Pipelined ADC)……… 53
第四章 管線式類比數位轉換器之設計與分析………………………… 55
4.1 簡介………………………………………………………………… 55
4.2 運算放大器 (Opamp)……………………………………………… 55
4.3 拔靴帶式開關電路 (Bootstrapped Switch Circuit) ……………… 61
4.4 米勒電容式取樣保持電路 (Miller-Capacitance-Based Sample and
Hold Circuit) ……………………………………………………… 64
4.5 1.5位元次類比數位轉換器 (1.5-bit Sub_ADC) ………………… 69
4.5.1 比較器電路 (Comparator Circuit)……………………………… 70
4.5.2 次類比數位轉換器之比較器電路……………………………… 76
4.5.3 解碼器電路 (Decoder) ………………………………………… 78
4.6 乘法式數位類比轉換器 (MDAC)………………………………… 79
4.7 數位錯誤校正電路 ………………………………………………… 86
4.8 暫存器電路 (Register) …………………………………………… 87
4.9 時脈產生器 (Clock Generator) …………………………………… 88
4.10 類比數位轉換器的測試方法 …………………………………… 90
4.11 管線式類比數位轉換器佈局前模擬結果 ……………………… 96
第五章 管線式類比數位轉換器之實體佈局考量……………………… 101
5.1 簡介………………………………………………………………… 101
5.2 基本實體佈局考量與技巧………………………………………… 101
5.3 類比積體電路的佈局……………………………………………… 103
5.4 實體電路佈局……………………………………………………… 105
5.4.1 運算放大器佈局………………………………………………… 105
5.4.2 拔靴帶式開關電路佈局………………………………………… 106
5.4.3 米勒電容式取樣保持電路佈局………………………………… 107
5.4.4 次類比數位轉換器佈局………………………………………… 107
5.4.5 乘法式數位類比轉換器佈局…………………………………… 108
5.4.6 單級類比數位轉換器佈局……………………………………… 108
5.4.7 D型正反器與全加器佈局……………………………………… 109
5.4.8 數位暫存器延遲電路佈局……………………………………… 109
5.4.9 數位錯誤校正電路的佈局……………………………………… 110
5.4.10 數位輸出暫存器電路的佈局 ………………………………… 110
5.4.11 九級管線式類比數位轉換器的佈局 ………………………… 110
5.5 管線式類比數位轉換器佈局後模擬結果………………………… 112
5.6 測試考量…………………………………………………………… 114
5.6.1 輸入終端電路 (Input Termination Circuit) …………………… 115
5.6.2 電源調節電路 (Power Regulator Circuit)……………………… 116
5.6.3 參考電壓產生器………………………………………………… 117
5.6.4 脈波產生器……………………………………………………… 118
第六章 結論及未來研究方向…………………………………………… 119
6.1 結論………………………………………………………………… 119
6.2 未來研究方向……………………………………………………… 120
參考文獻…………………………………………………………………… 121
簡歷………………………………………………………………………… 124

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