臺灣博碩士論文加值系統

發展至今的VLSI數位邏輯電路設計中，如何讓電路有較低的功率消耗、較短的延遲時間依然是電路設計者追求的主要目標。全加法器在數位系統中佔有極重要的地位，因此本論文將針對加法器做於主要探討方向。

過去一般傳統的加法器電路文獻之中，其主要的10-T（10-Transistor）架構為最精簡之設計。然而在加法器電路設計的歷史演化過程中;當隨著製程環境的改變，由於轉態電壓的不足，將導致電路輸出訊號有所錯誤。因此，在許多的文獻之中都已有探討到相關的改良方法。但是，美中不足的是這些的方法的消耗功率與速度上並非為最佳結果。

因此，本文改善並實現現有的加法器電路，可避免輸出訊號有錯誤並且提高輸出訊號之正確性。最後我們提出五種12-T（12-Transistor）電路架構並且與其他文獻的三種電路之架構做比較。

In VLSI digital logic circuit design, low power consumption and shorten delay time are still primary pursuit of the designers. Full adders is critical in digital systems. Thus, we try to focus on full adder design in this thesis.

Among all traditional adder archives, 10-T (10 Transistor) architecture is the most condensed design. However, the output signal can be erratic due to the change of process. Many literatures are discussing the corresponding improvements but none of these is the best result.

In this thesis, we try to improve the modern circuits to prevent signal error. Five 12-Tfull adders are proposed and comparison are made along with other three circuit architectures.

摘 要 iv
誌 謝 i
目 次 ii
表 目 錄 iv
圖 目 錄 vi
第一章 導論 1
1.1研究背景與動機 1
1.2研究目的 2
1.3章節結構 3
第二章 加法器文獻研究 4
2.1深次微米製程之電晶體探討 4
2.2加法器功率消耗探討 9
2.3加法器種類 11
2.3.1傳統加法器 11
2.3.1傳統加法器 12
2.3.2深次微米環境加法器 16
第三章 晶片架構設計 18
3.1架構簡介、原理 19
3.2加法器之基本元件 21
3.3加法器單元架構 22
第四章 晶片模擬結果 25
4.1模擬環境 25
4.2模擬結果 27
4.2.1傳統架構模擬 27
4.2.2傳統架構分析 30
4.3架構實現 46
4.3.1晶片規格表 47
4.3.2晶片設計流程 48
4.3.3晶片佈局平面圖 49
4.3.4晶片量測辦法 51
4.3.5晶片量測結果 52
4.3.6晶片顯微實照圖 54
第五章 總結與未來研究方向 55
5.1本論文研究之成果 55
5.2本論文研究之優點 55
5.3結論及未來方向 55
參考文獻 56

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