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研究生:廖青松
研究生(外文):Ching-Sung Liao
論文名稱:65 nm世代pMOSFETs的有效邊緣寬度及其在升溫熱載子加壓下之變化
論文名稱(外文):Effective Edge Width for 65 nm pMOSFETs and Their Variations under HC Stress at Elevated Temperature
指導教授:黃恆盛黃恆盛引用關係陳雙源陳雙源引用關係
指導教授(外文):Heng-Sheng HuangShuang-Yuan Chen
口試委員:王木俊劉傳璽
口試委員(外文):Mu-Chun wangChuan-His Liu
口試日期:2009-07-08
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:機電整合研究所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:67
中文關鍵詞:有效邊緣寬度溫度窄寬度可靠度淺溝槽絕緣邊緣熱載子
外文關鍵詞:effective edge widthTemperatureNarrow WidthReliabilityshallow trench isolation edgeHot Carrier
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就矽基半導體而言,由於電洞的平均自由徑較電子短,且遷移率也較電子差,在室溫約為電子的三分之一,所以在過去的研究中,皆認為nMOSFETs因熱載子所造成的特性劣化,遠比pMOSFETs嚴重。然而在電晶體進入深次微米及奈米尺度後,上述情況似乎已改變,而pMOSFETs的熱載子可靠度也成為一項新的問題。另外,現今CMOS技術中,淺溝槽絕緣(STI)不可避免地使用於電晶體之間,但其對於熱載子(hot-carrier)可靠度的影響,至今仍未確定,特別是窄寬度的pMOSFETs。
在本研究中,採用聯電65 nm製程,通道長度為0.06 μm,閘極氧化層為19.5 Å,寬度分別為10 μm、1 μm與0.12 μm之pMOSFETs作為實驗樣本,來進行通道熱載子(CHC)與汲極雪崩熱載子(DAHC)加壓測試,而測試的溫度分別是25℃、85℃與125℃三種。加壓實驗前後皆對電晶體量測I-V等特性,藉其物理特性、熱載子與窄寬度(narrow-width)效應,來了解電流衰退的情形,並計算有效邊緣寬度 (△w),對元件電性劣化的影響與了解其在升溫熱載子加壓下之變化。結果發現,與寬通道元件比較,窄通道pMOSFET之臨界電壓與汲極電流退化較嚴重,是因為STI邊緣區域的熱載子注入率較高,而使其電晶體性能加速退化。CHC也較DAHC嚴重,CHC加壓測試後,介面狀態和氧化層陷入電荷主要在STI邊緣與通到中心區域產生,而造成嚴重地臨界電壓漂移與汲極電流劣化。從實驗結果發現,△w是在臨界電壓與汲極電流劣化中佔主要因素,因此,窄通道元件比寬通道元件更加劣化。
On the basis of the semiconductor of silicon, the mean free path of holes is shorter than electrons, and hole’s mobility is slower than electrons about one third of the electrons at the room temperature. Therefore, the hot-carrier inducing characteristic degradation in nMOSFETs was considered much more severely than that in pMOSFETs. However, as the transistor channel length has been scaled down into deep submicron and nano scale, the previous concepts may not valid again and the hot-carrier reliability of pMOSFETs has gradually become a significant issue. In addition, shallow trench isolation (STI) is inevitable to be used in isolating the between transistors in today COMS technology on the narrow width pMOSFETs.
In the work, pMOSFETs on wafers from 65nm node of UMC were characterized. The pMOSFETs used in this experiments have W=10 μm, 1 μm and 0.12 μm with 19.5 Å gate oxide thickness, all the Lg=0.06 μm. The devices were stressed under channel hot-carrier (CHC) and drain avalanche hot-carrier (DAHC) condition at temperatures of 25, 85 and 125 ℃. After experiments, I-V measurements were used to characterize the physical properties, hot-carrier effect and narrow-width effect. It can understand from current degradation, and calculated the effective edge width (△w), that is discussed on affected electrical characteristics degradation, and realized their variations under HC stress at elevated temperature. Comparing with the wide width pMOSFET, the experimental results discovered that the narrow width pMOSFET have more degradation of threshold voltage and drain current. It is believe that the transistor characteristic accelerate degradation due to have higher the hot-carrier injection (HCI) rate at STI edges region. CHC stress results more serious degradation than DAHC too. It consider that CHC stress produce interface states and oxide trapped charges both on STI edges and channel center region, causing threshold voltage shifts and drain current degradation seriously. From the experimental result, the degradation in threshold voltage and drain current are dominated by △w, and hence the narrow width device presented the worse degradation than wide width one.
ABSTRACT (CHINESE)...........................................................................................i
ABSTRACT (ENGLISH).........................................................................................iii
ACKNOWLEDGEMENTS........................................................................................v
CONTENTS.............................................................................................................vi
LIST OF TABLES..................................................................................................viii
LIST OF FIGURES..................................................................................................ix

1 INTRODUCTION
1.1 Background and Motivation..............................................................................1
1.2 Thesis Organization............................................................................................2

2 BASICS ABOUT HOT-CARRIER RELIABILITY
2.1 Research about Hot Carrier Effect.......................................................................3
2.1.1 Hot carrier effect.......................................................................................3
2.2.2 Mechanisms...............................................................................................7
2.2.3 Temperature effect....................................................................................19
2.3 Narrow Width Effect and Reverse Narrow Width Effect....................................20
2.4 Shallow Trench Isolation (STI) Edge Effect.......................................................23

3 EXPERIMENTS
3.1 Experimental Structures....................................................................................28
3.2 Stress Methods.................................................................................................29
3.3 Device Fabrication...........................................................................................29
3.4 Stress Conditions and Measurement Conditions.................................................30

4 RESULTS AND DISCUSSION
4.1 Basic VTH and I-V Characteristics for pMOSFET Devices …………..................35
4.2 Device Degradation at Elevated Temperature for pMOSFET under CHC............37
4.2.1 VTH shift degradation................................................................................37
4.2.2 ID,lin degradation......................................................................................40
4.2.3 ID,sat degradation.......................................................................................43
4.3 Comparison PMOSFETs under Two Stress Modes.............................................46
4.4 Calculating the Effective Edge Width (Δw)......................................................48
4.5 The Relationship between Effective Edge Width and CHC Stress Bode..............52
4.6 Comparison the Effective Edge Width Dependant on Stress Time and Temperature………………………………………………………………………59

5 CONCLUSION AND FUTURE WORKS
5.1 Conclusions......................................................................................................61
5.2 Future Works....................................................................................................62

REFERENCES.......................................................................................................63
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