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[1]S. S Chung, S. J. Yang, and J. J. Yang, “A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices,” Proc. Int. Reliability Physics Symp., 2001, pp. 419-424. [2]S. S. Chung, S. Jr. Chen, W. J. Yang, C. M. Yih, and J. J. Yang, “New degradation mechanisms of width-dependent hot carrier effect in quarter-micron shallow-trench-isolated p-channel metal-oxide-semiconductor field-effect- transistors,” Japanese Journal of Applied Physics, vol. 40, January 2001, pp. 69-74. [3]F. Matsuoka, H. Iwai, H. Hayashida, K. Hama, Y. Toyoshima and K. Maeguchi, “Analysis of hot-carrier-induced degradation mode on pMOSFET's,” IEEE Translations on Electron Devices, vol. 37, June 1990, p.1487. [4]E. Li, E. Rosenbaum, J. Tao, G. C-F Yeap, M. R. Lin, and P. Fang, “Hot carrier effects in nMOSFETs in 0.1m CMOS technology,” Proc. Int. Reliability Physics Symp., 1999, pp. 253-258. [5]D. K. Schroder, Semiconductor material and device characterization, New York Wiley, 2006, Ch. 12, p. 701. [6]A. Schwerin, W. Hansch, and W. Weber, “The relationship between oxide charge and device degradation: A comparative study of n- and p-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 12, Dec. 1987, pp. 2493-2500. [7]W. Shockley, “Problems related to p-n junction in silicon,” Solid-State Electron, vol. 2, 1961, pp. 35-67. [8]C. Hu, “Lucky-electron model of channel hot electron emission,” International Electron Devices Meeting, vol. 25, 1979, pp. 22-25. [9]S. Tam, P. K. Ko, and C. Hu, “Lucky-electron model of channel hot electron rejection in MOSFET’s,” IEEE Trans. Electron Devices, Sept. 1984, pp. 1116-1125. [10]C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chen, and K. W. Terrill, “Hot-electron-induced MOSFET degradation-model, monitor, and improvement,” IEEE Trans. Electron Devices, vol. ED-32, Feb. 1985, pp. 375-385. [11]K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n- and p-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-30, August 1983, pp. 871-876. [12]Renesas Technology Corp, Semiconductor reliability handbook, 2006, pp. 110. [13]J. J. Sanchez, “Review of carrier injection in the silicon/silicon-dioxide system,” IEE Proceedings G, vol. 138, No. 3, June 1991, pp. 377-389. [14]H. Iwai, M. R. Pinto, C. S. Rafferty, J. E. Oristian, R. W. Dutton, “Analysis of velocity saturation and other effects on short-channel MOS transistor capacitances,” IEEE Translations on Computer-Aided Design, vol. CAD-6, no. 2, March 1987, pp. 173-184. [15]S. Wolf, Silicon processing for the VLSI era, vol.3-The submicron MOSFET, Ch 7, Thin gate oxides-growth and reliability, 1995, Lattice press. [16]E. Murakami, T. Yoshimura, Y. Goto, S. Kimura, “Gate length scalability of n-MOSFET's down to 30 nm comparison between LDD and non-LDD structures,” IEEE Trans. Electron Devices, vol. 47, no. 4, April 2000, pp. 835-840. [17]W. Wang, J. Tao and P. Fang, “Dependence of HCI mechanism on temperature for 0.18 μm technology and beyond”, IEEE IRW, Final Report, 1999, pp. 66-68. [18]S. Chung and C. T. Li, “An analytical threshold-voltage model of trench-isolated MOS devices with nonuniformly doped substrates,” IEEE Trans. Electron Devices, vol. 39, Mar. 1992, pp. 614-622. [19]D. Fotty, MOSFET Modeling with SPICE, Englewood Cliffs, NJ: Prentice-Hall, 1997, Ch. 6, pp. 113-115. [20]BSIM Group, MOSFET Model. Univ. California, Berkeley. (online available: http://www-device.eecs.berkeley.edu/~bsim3/) [21]D. Fotty, MOSFET Modeling with SPICE, Englewood Cliffs, NJ: Prentice-Hall, 1997, Ch. 11, p. 399. [22]J. Mandelman and J. Alsmeir, “Anomalous narrow channel effect in trench-isolated buried channel P-Mosfets,” IEEE Electron Device Lett., vol. 15, Dec. 1994, pp. 496–498. [23]B. S. Doyle, R. S. Oconnor, K. R. Mistry, and G. J. Grula, “Comparison of Shallow Trench and LOCOS Isolation for Hot-Carrier Resistance,” IEEE Electron Device Lett, vol. 12, no. 12, Dec 1991, pp. 673-675. [24]M. Nishigohri et al., “Anomalous hot-carrier induced degradation in very narrow channel nMOSFET’s with STI structure,” IEEE IEDM Tech. Dig., Dec. 1996, pp. 881-884. [25]J. F. Chen, K. Ishimaru, and C. Hu, “Enhanced hot-carrier induced degradation in shallow trench isolated narrow channel pMOSFET’s,” IEEE Electron Device Lett, vol. 19, no. 9, Sep 1998, pp. 332-334 [26]W. Lee, S. Lee, T. Ahn, and H. Hwang, “Degradation of hot carrier lifetime for narrow width MOSFET with shallow trench isolation,” IEEE Proceedings of International Reliability Physics symposium, 1999, pp. 259-262. [27]S. S. Chung et al., “Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O Gate Stack,” IEEE Transactions on Device and Materials Reliability, vol. 6, no. 1, March 2006, pp. 95-101. [28]M. J. Deen, Z. P. Zuo, “Edge effects in narrow-width MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, no. 8, August 1991, pp. 1815-1819. [29]S. Y. Chen, et al, “Investigation of DC hot-carrier degradation at elevated temperatures for p-Channel metal–oxide–semiconductor field-effect transistors of 0.13 [30]S. S. Chung et al., “The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology,” Proceedings of 11th IPFA, July 2004, pp. 279-282.
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