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研究生:胡慶源
研究生(外文):Ching-Yuan Hu
論文名稱:嵌入式多處理器FPGA系統之改良式模擬退火軟硬體分割演算法
論文名稱(外文):Enhancement of Simulated Annealing Algorithm for Hardware-Software Partitioning on Embedded Multiprocessor FPGA Systems
指導教授:李宗演李宗演引用關係
指導教授(外文):Trong-Yen Lee
口試委員:蔡加春熊博安
口試委員(外文):Chia-Chun TsaiPao-Ann Hsiung
口試日期:2008-12-18
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電資碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:59
中文關鍵詞:軟硬體分割模擬退火演算法基因演算法多處理器
外文關鍵詞:Hardware/Software PartitioningSimulated Annealing AlgorithmGenetic AlgorithmMulti-processor
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未來資訊產品的趨勢是低功率消耗、低成本及高執行效率。本文提出改良式模擬退火演算法(Enhancement of Simulated Annealing Algorithm, ESA)來達到一個應用在嵌入式系統多處理機架構下之的軟硬體分割要求,以滿足系統設計時可達成低功率消耗、低成本及高效能的需求。而本文基於模擬退火演算(Simulated Annealing Algorithm, SA)的基本架構,提出平衡功率消耗、成本、效能之需求的成本函數(Cost function),且改良演算法的求解方式,使得演算法所需的模擬時間比原模擬退火演算減少64%模擬時間,與基因演算法(Genetic Algorithm)相比,則是減少115%模擬時間。本文以兩個範例分別為自適應差分脈衝編碼調制(Adaptive Pulse Code Modulation,ADPCM)系統及JPEG (Joint Photographic Experts Group)影像壓縮編碼系統來驗證演算法的效能。而若使用改良式模擬退火演算法,並以JPEG為範例去找出最佳的軟硬體分割結果,可以找出三顆處理器(Processor)為最佳的處理器之個數,且與只使用兩顆處理器相較起來, 在滿足系統限制下,減少了132%的邏輯元件,且在功率消耗上也減少了162%。
The trend of information product is requiring low power consumption, low cost and high performance. In this thesis, we propose an Enhancement of Simulated Annealing Algorithm (ESA) to meet the requirements of low power consumption, low cost and high performance for embedded multiprocessor FPGA system. A cost function based on simulated annealing is proposed to balance between power, cost and performance requirements. Experimental results shown that the simulation time of proposed algorithm is reduced by 64% than original simulated annealing algorithm and 115% than Genetic Algorithm. In this thesis, we use two examples, ADPCM and JPEG, to verify the performance of proposed algorithm. If we use Enhancement of Simulated Annealing algorithm to search for the best solution for JPEG hardware software partitioning, the experimental results shown that using three processors is the optimal. To compare experimental results under two processors and system constraints, JEPG system design have 132% reduced logic elements and 162% power consumption by proposed ESA algorithm.
目 錄

中文摘要 i
英文摘要 ii
致謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 導論 1
1.1簡介 1
1.2研究動機與目的 2
1.3本論文之貢獻 4
1.4論文架構 4
第二章 相關文獻探討 5
2.1相關的軟硬體分割技術 6
2.2 嵌入式多處理機FPGA系統的相關研究 8
第三章 軟硬體分割方法 9
3.1 CDFG(Control and Data Flow Graph)介紹 9
3.2模擬退火軟硬體分割演算法 11
3.3 改良式模擬退火軟硬體分割演算法 17
3.3.1演算法系統模型 17
3.3.2演算法成本函數 18
3.3.3演算法流程 20
3.4演算法差異性比較與分析 25
第四章 使用者圖形介面設計 27
4.1 工具介面操作介紹 28
4.2 簡單的範例介紹 30
第五章 實驗結果與分析 35
5.1 自適應差分脈衝編碼調製系統之軟硬體分割 36
5.1.1 ADPCM軟硬體分割演算法效能分析 37
5.2 JPEG影像壓縮編碼系統之軟硬體分割 38
5.2.1 JPEG軟硬體分割演算法效能分析 40
5.3 權重值(Weight value)影響分析 43
5.4 多處理器之優勢分析 43
5.5 功率消耗(Power Consumption)估算說明 45

第六章 結論 46
參考文獻 47

附錄: 已刊登或接受之論文
1. 李宗演、胡慶源、范揚興、蔡加春, “應用於嵌入式多處理機系統之模擬退火
軟硬體分割演算法,” Workshop on Consumer Electronics 2008, Taipei Taiwan, pp. 407-414, Dec. 5, 2008……….………………………………………………....51
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