本論文中利用TSMC 0.18μm 1P6M mixed signal的製程來完成一個10位元管線式類比數位轉換器之設計模擬，其取樣頻率為40MHz，使用的供給電壓為1.8V。本次設計為九級(stage)的管線式類比數位轉換器，前八級採用1.5-bit/per stage的技術，最後一級則為一個2-bit的快閃式類比數位轉換器。整體電路的設計採用全差動的架構來降低雜訊的干擾。
在電路模擬方面，我們利用HSPICE來進行模擬，使用了台積電0.18微米互補式金氧半製程設計，對於10位元40MHz管線式類比數位轉換器的模擬結果如下：在輸入0.5078125MHz的正弦波時，訊號對雜訊比(SNR)為57.8dB，有效位元數(ENOB)為9.32位元，電路的功率消耗為117mW。

In this thesis, we design a 10-bit 40MSample/s pipelined analog-to-digital converter (ADC) by TSMC 0.18μm 1P6M mixed signal process technology. The supply voltage is 1.8V. The ADC architecture is nine stage pipelined ADC in this design, we adopt 1.5-bit/per stage architecture and a 2-bit flash ADC in the last stage. In order to decrease noise interference, the whole circuit is designed by fully differential structure.
The ADC is simulated by HSPICE using TSMC 0.18μm 1P6M mixed signal process technology. The proposed ADC has the following performances: For 0.5078125MHz sine wave input, the SNR is 57.8dB, the ENOB is 9.32bits, and the power consumption is 117mW at the maximum conversion rate.

ABSTRACT i
中文摘要 ii
致謝 iii
章節目錄 iv
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1 研究動機 1
1.2 論文結構 2
第二章 高速類比數位轉換器架構概論 3
2.1 簡介 3
2.2 類比數位轉換器之架構介紹 3
2.2.1 快閃式類比數位轉換器(Flash ADC) 3
2.2.2 兩階段快閃式類比數位轉換器(Two-Step Flash ADC) 5
2.2.3管線式類比數位轉換器(Pipeline analog to digital converter) 6
2.3類比數位轉換器特性參數 8
2.3.1動態性能(Dynamic Performance) 8
2.3.2 靜態性能(Static Performance) 12
第三章 全差動運算放大器之設計 16
3.1簡介 16
3.2運算放大器基礎架構 18
3.2.1 增益增強型(gain-boosting)運算放大器架構 18
3.2.2 軌對軌（rail-to-rail）架構 20
3.3主要級和增益級運算放大器電路 22
3.3.1 增益級運算放大器電路 22
3.3.2 主要級運算放大器電路 23
3.3.3 共模回授電路 24
3.3.4 偏壓電路 26
3.4 運算放大器所需之規格 27
3.5 運算放大器之模擬結果 32
第四章 管線式類比數位轉換器之分析與設計 34
4.1比較器電路 34
4.2 子類比數位轉換器(sub-ADC) 37
4.2.1 1.5-bit子類比數位轉換器(sub-ADC) 37
4.2.2 2-bit子類比數位轉換器(sub-ADC) 39
4.3 DAC/減法器/增益級(Multiplying DAC, MDAC) 40
4.4 時脈產生器(Clock Generator) 44
4.5 暫存器(Register) 46
4.6 加法器(Adder) 47
4.7 10-bit 管線式ADC模擬結果 49
第五章 結論與未來工作 53
參考文獻 54

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