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研究生:吳信彥
研究生(外文):Hsin-Yen Wu
論文名稱:以FPGA實現移動適應性解交錯於弱視輔具之設計
論文名稱(外文):Design and Implementation of Motion-Adaptive De-Interlacing for Low Vision Aid on FPGA
指導教授:張寅張寅引用關係
指導教授(外文):Yin Chang
學位類別:碩士
校院名稱:國立陽明大學
系所名稱:醫學工程研究所
學門:工程學門
學類:生醫工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:68
中文關鍵詞:解交錯FPGA交錯式掃描漸進式掃描弱視輔具
外文關鍵詞:De-interlaceFPGAInterlacedProgressivelow vision aid
相關次數:
  • 被引用被引用:2
  • 點閱點閱:252
  • 評分評分:
  • 下載下載:52
  • 收藏至我的研究室書目清單書目收藏:2
目的:透過解交錯(De-interlace)方式,將弱視輔具之交錯式(Interlaced)掃描的影像來源訊號轉換成漸進式(Progressive)掃描的影像訊號並以FPGA實現。藉此作法以消除許多視覺上的不良效應,如邊緣閃爍、線條抖動、鋸齒效應等等。
方法:目前一般解交錯的主要方式有二:一為空間域的插補(Spatial Interpolation),另一則為時間域上的插補(Temporal Interpolation),它們各有優點與瓶頸。為此我們提出了改良方案:移動適應性的解交錯方式,它可以結合空間域上內插及時間域上內插的優點。本研究主要包括三大部分:移動偵測(Motion Detection)、空間內插、時間內插。移動偵測考慮了四張圖場(Field)來做運動與否的判斷;空間內插考慮了3x2的Block範圍,並提出沿著邊緣內插來消除不良視覺的效應;時間內插則是用前後張場畫面的像素點來做內插。搭配ALTERA Cyclone® II EP2C70現場可規劃邏輯陣列(Field Programmable Gate Array, FPGA)其可重複規劃硬體及把系統實現於單一晶片裡之特性來設計數位電路,並結合影像強化處理演算法,能快速發展與實現弱視者所需之即時影像強化系統。
結果:由FPGA實現移動適應性解交錯處理的結果得知,經由數位電路在時脈27 MHz下做運算後,將大小640×480、解析度8位元之影像經過解交錯後得到良好品質影像,搭配影像強化電路可以達到每秒64張強化影像輸出。
結論:本論文所採用的移動適應性解交錯演算法對一般的自然影像都有不錯的效果,去除了我們所不願意見到的不良畫面,並以FPGA實現數位硬體電路,使得系統的影像輸入有一個好的影像來源,結合前人的補償策略及影像強化電路,建立了一套完整的弱視輔具系統。
關鍵字:解交錯、FPGA、交錯式掃描、漸進式掃描、弱視輔具
Objective:Transforing the interlaced video signal for the low vision aid to the progressive video signal with the technique called de-interlacing and implement on FPGA. This method would eliminate undesirable visual artifacts such as line flicker, twitter, line crawling, sawtooth effect, etc.
Method:There are two major approaches for de-interlacing: Spatial Interpolation and Temporal Interpolation. Each of them has its advantages and bottlenecks in performance. That leads us to bring out a new idea which may overcome the defects that have been existed in these two types of prosthesis and improve the overall performance: Motion Adaptive De-Interlacing. It includes both advantages of Spatial Interpolation and Temporal Interpolation. This research mainly includes three major parts: Motion Detector, Spatial Interpolation and Temporal Interpolation. Motion Detector considers the information of 4 fields to jadge if the video is motion or not. Spatial Interpolation considers 3x2 block range and proposes that extend the edge of the interpolation to eliminate bad visual the effect. Temporal Inetrpolation interpolate with neighboring 2 fields. Through the algorithm of de-interlacing that incorporated with FPGA (Field Programmable Gate Array, ALTERA Cyclone® II EP2C70), which can integrate system on a programmable chip, a high-speed image enhancement system can be implemented
Result:The results of de-interlacing through the application of FPGA showed that when the system clock ran at 27 MHz, then for a nice image with size of 640×480 and 8-bit resolution that was performanced, combine with the image enhancement circuit, the enhanced-image output can reach 64 frames/sec.
Conclusion:Most image processed by Motion Adaptive De-Interlacing which this research proposed performance well. This method eliminates undesirable visual artifacts and implement on FPGA. It makes the video input has a good video source and combine with predecessor’s image Enhancement circuit to establish a complete system of low vision aid
Keywords:FPGA、low vision aid、De-interlace、Interlaced、Progressive
中文摘要 I
ABSTRACT II
目錄 IV
圖目錄 VI
表目錄 VIII
第一章 緒論 1
1-1論文架構 1
1-2前言 1
1-3研究動機 2
1-4研究流程 3
第二章 理論及相關研究 4
2-1解交錯 4
2-1.1背景 4
2-1.2 解交錯處理的必要性 5
2-1.3相關技術 7
2-2空間域的解交錯演算法 7
2-3時間域的解交錯演算法 11
2-4移動適應性解交錯演算法 12
2-5移動補償解交錯演算法 14
第三章 演算法設計 16
3-1 移動適應性解交錯演算法架構 16
3-2 四圖場移動偵測架構 18
3-2 空間域及時間域上的解交錯 21
3-2.1 空間上的解交錯(Spatial Interpolation) 21
3-2.2 時間上的解交錯(Temporal Interpolation) 23
第四章 演算法的實現 25
4-1 設計方式 25
4-2 設計層次 28
4-3 設計流程 29
第五章 數位電路架構與系統 31
5-1 ITU-R 656解碼電路 32
5-2 移動適應性解交錯電路 37
5-3 色彩空間轉換電路 40
5-4 顯示時序控制電路 43
5-5 系統硬體 47
第六章 結果 49
6-1 各種演算法的驗證與分析 49
6-1.1 空間域的解交錯演算法分析 50
6-1.2 各範圍ELA解交錯演算法分析 53
6-1.3 時間域的解交錯演算法分析 54
6-1.4 同時考慮空間域及時間域上插補的演算法分析 55
6.2 數位電路合成之結果 57
第七章 討論 59
7-1 解交錯處理 59
7-2 攝影機之解析度品質 61
7.3 數位電路架構 61
7.4 即時影像 62
第八章 結論與未來展望 64
參考文獻 65
附錄 A 67
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