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研究生:林正基
研究生(外文):Chung-chi Lin
論文名稱:數位影像之解交錯及解析度伸展的即時系統研究
論文名稱(外文):The Real-time System Design of Video De-interlacing and Digital Image Scaling
指導教授:江煥鏗許明華許明華引用關係
學位類別:博士
校院名稱:國立雲林科技大學
系所名稱:工程科技研究所博士班
學門:工程學門
學類:綜合工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:118
中文關鍵詞:超大型積體電路設計影像插補解交錯影像伸展
外文關鍵詞:de-interlacingscalinginterpolationVLSI design
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科技的進步使得多媒體顯示器,如:HDTV、PDP、LCD等循序式的高畫質顯示器已取代傳統電視機。為了將解交錯式影像資訊轉換到這些循序式的顯示器上播放時,能有效改善影像畫面資訊插補錯誤等問題。因此,在本論文中我們提出兩個解交錯的方法,分別為多方向性偵測及場景變化偵測。其中多方向性偵測主要是偵測不同的方向及角度來找出一個最佳的方向解,然後,再來選擇最適當的資訊來進行插補。另一個方法,則是針對場與場間的變化來進行偵測,過去許多解交錯的演算法往往只是考量視覺上的影像品質而來加以改善,並沒有考慮到場景變化所造成的影像問題,因此我們提出此問題來加以改善。由於,這演算法運算複雜度相當龐大,使得運算時無法達到即時的處理,因此我們將這演算法設計出硬體架構來改善執行速度的問題,並且使用FPGA來實現且驗證,最後並完成此系統之VLSI晶片設計。

然而循序式數位影像的普及性與多媒體顯示器製造技術不斷的進步,數位顯示器的解析度規格也愈趨多樣性,因此如何將數位影像於不同解析度規格之間做轉換並且在維持其高影像品質的同時兼顧低運算成本便是一個重要解決的課題。本論文將針對影像解析度縮放時必須使用的影像插補演算法進行探討,共有兩個主軸:第一針對廣為使用的雙立方插補法進行記憶體讀取次數的降低及設計出高效能、低硬體成本與高使用彈性的電路架構,以改良其令人詬病的高運算量問題;第二則是提出一個嶄新的影像插補演算法,此插補法不僅能擁有接近雙立方插補法的影像插補品質,且僅需使用更低的運算量及硬體電路成本,並且能夠實現於上述的電路架構中。為了驗證與檢視所提出的影像插補演算法及電路架構,因此使用FPGA與雛型開發平台進行影像縮放雛型系統設計與驗證。最後透過VLSI設計流程完成影像插補電路的VLSI晶片。
The current NTSC system uses the interlaced scan technique to display video sequence. The technique creates undesirable visual artifacts and makes the lines flicker, twitter, and crawl. On the other hand, it is unsuitable for devices like LCD displays, personal computer monitors, and HDTV that require a progressive scan format. Thus, video de-interlacing techniques, which convert the format of interlaced images to progressive images, are important today to improve the quality of display. In this dissertation, we propose two video de-interlacing methods to reduce jagged effect, blurred effect, and artifacts effect in display and improve the quality of pictures. At first, motion adaptive de-interlacing with horizontal and vertical motions detection is presented. In this method, de-interlacing begins with object motion detection, which is to ensure that the inter-field information is used precisely, which is capable of improving the quality of the visual results. Then, an efficient video de-interlacing technique with scene change detection and its VLSI architecture design is proposed. Most of de-interlacing techniques are capable of improving the quality of the visual results; nevertheless, their performances are seriously affected by scene change. To improve the quality of de-interlacing, the factors of scene change are taken into account when de-interlacing techniques are applied. Based on our approach, the high performance VLSI architecture has been designed and verified by FPGA, and then implemented with UMC 0.18um CMOS standard cell.
As progressive video displays become more popular, the technique of improving resolution for digital displays is more important. Therefore, converting images to different resolutions while maintaining their high quality and low operation cost at the same time become a significant issue. This thesis presents two theoretical agendas for the study of image interpolation algorithm for image scaling. First, a high-speed architecture of bi-cubic convolution interpolation is introduced to reduce the computational complexity of generating weighting coefficients and number of memory access times. Further, it attempts to minimize the error propagation which results from the fraction truncations when calculating pixel coordinates under fixed-point operations. Error propagation significantly diminishes the output image quality for hardware interpolation. In order to avoid the inaccuracy accumulation, a simple periodical compensation technique is presented to improve the average Root-Mean-Square Error (RMSE) significantly. From the perspective of hardware cost, the presented architecture saves about 50% cost compared to the latest bi-cubic hardware design work. The architecture was implemented on the Virtex-II FPGA, and the high-speed VLSI has been successfully designed and implemented with TSMC 0.13μm standard cell library. Secondly, a novel image interpolation method, extended linear interpolation, is presented. It is an efficient method with interpolation quality compatible to that of bi-cubic convolution interpolation. Based on the approach, the efficient hardware architecture was designed under real-time requirement. Compared to the latest bi-cubic hardware design work, the architecture saves about 60% of hardware cost. The architecture was implemented on the Virtex-II FPGA, and the high-speed VLSI has been successfully designed and implemented with TSMC 0.13μm standard cell library.
1. Introduction…………………………………………………………….1
1.1. Video De-interlacing………………………………………………1
1.1.1. Intra-field De-interlacing………………………………. …3
1.1.2. Inter-field De-interlacing…………………………………..5
1.1.3. Motion Adaptive De-interlacing……………………………6
1.1.4. Motion Compensated De-interlacing………………………8
1.2. Digital Image Scaling……………………………………………8
1.2.1. Nearest-neighbor Interpolation……………………………10
1.2.2. Bi-linear Interpolation…………………………………….12
1.2.3. Winscale Interpolation…………………………………….14
1.2.4. Cubic Polynomial Interpolation…………………………..17
1.3. Motivation……………………………………………………….20

2. Motion Adaptive De-interlacing with Multi-direction Detection……..22
2.1. Algorithm…………………………………………………….......22
2.2. Simulation Results………………………………………………..27

3. Motion Adaptive De-interlacing with Reliable Inter-field Information.31
3.1. Algorithm……………………………………………… . …….31
3.2. Architecture………………………………………………………33
3.2.1. Architecture of Scene Change Detection………………….35
3.2.2. Architecture of ST-ELA………………… …………….36
3.3. Simulation Results………………………………………………..39

4. High-performance Architecture Design of Bi-cubic Interpolation……47
4.1. Design Method Analysis…………………………………………47
4.1.1. Coordinate Orientation and Interval Calculation………….48
4.1.2. Reduction of Weighting Coefficient Computation………...50
4.1.3. Decrease of Number of Memory Accesses………………..52
4.2. Architecture………………………………………………………53
4.2.1. Coordinate Orientation Unit……………………………….54
4.2.2. Weighting Coefficient Generator………………………….56
4.2.3. Vertical and Horizontal Interpolation Units……………….57
4.2.4. Virtual Pixel Buffer………………………………………..59
4.3. Error Compensation for Interpolated Coordinates……………….60
4.4. Simulation Results………………………………………………..64
4.5. Summary………………………………………………………….72

5. Efficient Architecture Design of Extended Linear Interpolation……...74
5.1. Kernel of Extended Linear Interpolation…………………………74
5.2. Architecture of Weighting Coefficient Generator…………..……76
5.3. Simulation Results………………………………………………..80
5.4. Summary………………………………………………………….85

6. Conclusions and Future Work…………………………………………87

Reference………………………………………………………………….92
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