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研究生:趙偉翔
研究生(外文):Wei-Hsiang Chao
論文名稱:權重式仲裁之階層化CICQ交換器模擬與系統晶片微網路實現
論文名稱(外文):Weighted Arbitration for Hierarchical CICQ Switch Simulation and On-Chip Network Implementation
指導教授:許明華許明華引用關係
指導教授(外文):Ming-hwa Sheu
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:112
中文關鍵詞:CICQ權重式NOC階層式
外文關鍵詞:HierarchicalWeightedCICQNOC
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隨著晶片製程的發展,單一晶片上所能容納的功能元件(IP)日益增多,利用晶片微網路傳送資料已成為研究重點,每個IP的資料流量需求都不一樣,但是頻寬卻是固定的,所以發展出一個高效率排程傳輸系統是必須的。

本篇論文提出一個高效率的晶片內階層式CICQ交換器設計,同時搭配ㄧ具權重式仲裁機制之仲裁器,此階層式架構具有低面積消耗優點,而權重仲裁器以兩輸入資訊做排程,不會隨著交換器埠數的增加而改變仲裁器的複雜度。為了呈現交換器的效能,經由SystemC 來模擬CICQ交換器的效能。在內部buffer size相同下,我們交換器在資料產出率方面比傳統CICQ架構與輸入分享式CICQ架構相比,最多增加了11.2%。在average delay方面,本架構buffer size為1時,delay效能與其他權重仲裁器buffer size為8時相當。

所提出之架構已在Altera Stratix II FPGA驗證傳輸效能,最高速度可達320MHz,且使用TSMC 0.13奈米製程下線一顆交換電路面積為1.658 x 1.658mm2,消耗功率為36.66mW,經實際量測速度為133MHz,最後我們將switch與鎖相迴路整合在一起,使資料交換的速度可達10Gbps。
In accordance with the development of system on chip, more and more functional components have to be integrated at the single chip. Using NOC transmits data is one of the key techniques for fast data-transfer research. The data rates of all IP in NOC are different, but the bandwidth of data link is fixed. It is necessary to develop an efficient switch and network system which have high performance schedule for data exchange.

In this thesis, a hierarchical CICQ switch with weight priority arbiter has been proposed and designed. The hierarchical structure possesses lower buffer size, simpler data scheduler. Each weighting arbiter only tackles the information of two queues, and it does not change the design complexity as increasing the number of switch port. In order to demonstrate the performance, SystemC is used to simulate CICQ switch. Based on the same internal buffer size, the throughput of our design can increase the data throughput rate up to 11.2% than the traditional CICQ and input- shared CICQ architecture. For the average delay, our architecture is better than other weighting arbiter under the same internal buffer size.

The proposed switch architecture has been implemented and verified in Altera Stratix II FPGA, and its operating speed achieves 320MHz. Finally, the switch chip is also fabricated by TSMC 0.13um CMOS processes. Its area occupies 1.658 x 1.658mm2 silicon area and the power consumption is about 36.66mW. After chip measurement, the working speed is at 133MHz. At last, we integrate the switch and PLL in chip, the internal operation speed can reach 10Gbps.
中文摘要....................................i
英文摘要....................................iii
致謝.........................................iv
目錄........................................v
表目錄......................................vii
圖目錄....................................viii
第一章 序論..................................1
1.1、研究動機............................1
1.2、研究目標............................2
1.3、論文架構............................2
第二章、晶片微網路背景介紹及相關研究.........4
2.1、何謂晶片微網路(Network on Chip).....4
2.2、晶片微網路相關議題探討..............8
2.2.1、網路拓撲........................8
2.2.2、繞徑方式(Routing Algorithm)....11
2.2.3、資料交換方式...................15
2.2.4、封包格式.......................18
2.2.5、流量控制機制...................19
2.2.6、交換電路、排程器及其演算法.....20
2.3、交換電路介紹及相關研究.............21
2.3.1、交換電路演進...................21
2.3.2、CICQ交換電路相關問題探討.......26
2.3.3、priority scheduler優缺點介紹...29
第三章、高速階層式CICQ系統晶片微網路架構設計33
3.1、高速階層式CICQ系統晶片微網路架構設計方式..........................................33
3.1.1、交換電路硬體架構...............33
3.1.2、階層式交換電路硬體架構.........35
3.2、輸入traffic權重式仲裁器演算法與排程器架構..........................................36
3.2.1、仲裁器整體硬體架構.............36
3.3、模擬環境...........................40
3.3.1、模擬環境與訊務介紹.............40
3.4、模擬結果與比較.....................42
第四章、晶片實現............................49
4.1、晶片測試規劃.......................49
4.2、FPGA配合PG和LA驗證.................57
4.3、影像驗證...........................62
4.4、晶片合成與Gate-Level模擬驗證.......64
4.5、佈局圖與Post-Layout模擬驗證........65
4.6、晶片下線量測.......................70
4.6.1、Test Plan、design a DUT Boar、Pin Configuration...............................72
4.6.2、Level Setup....................74
4.6.3、Timing and Vector Setup........75
4.6.4、Functional Test................75
4.6.5、Shmoo Plot.....................80
4.7、整合PLL、10Gbps與微網路交換器晶片測試規劃..........................................82
4.7.1、測試考量.......................85
4.7.2、模擬結果.......................87
4.8、整合PLL、10Gbps交換電路與微網路交換器晶片實現與測量..................................89
第五章、結論
5.1、總結...............................96
5.2、未來方向...........................96
參考文獻....................................98
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