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研究生:葉欣錩
研究生(外文):Hsin-Chang Yeh
論文名稱:嵌入式即時影像物件切割之軟硬體協同設計
論文名稱(外文):Hardware/Software Co-design for Real-Time Image Object Segmentation in Embedded System
指導教授:許明華許明華引用關係
指導教授(外文):Ming-Hwa Sheu
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:164
中文關鍵詞:軟硬體協同設計物件切割矽智產連接區域標籤化驅動程式
外文關鍵詞:SIPHardware/Software Co-DesignLinux Device DriverConnected Component LabelingObject Segmentation
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近年來,嵌入式SOC(system-on-a-chip)系統晶片日趨成熟且功能複雜,而SOC整合設計可透過嵌入式系統來做軟/硬體協同設計來達成。而影像物件切割技術,可被整合在嵌入式SOC系統當中,像是具有視訊影像分析功能的智慧型網路攝影機(IP camera)。
本論文為一套具有背景更新功能的即時影像物件切割嵌入式系統,本系統使用軟/硬體整合設計方法,並使用的ARM+FPGA發展板實現整個嵌入式系統,所以針對影像物件切割系統內運算量較大的影像運算處理部分,設計硬體加速系統處理速度來達到即時影像物件切割。其中將物件切割演算法其中的連接物標籤化處理和其他運算量大的部份做成矽智產(SIP,Silicon Intellectual Property),並符合AMBA晶片匯流排規格設計。在作業系統軟體狀態資源下,修改出可供使用的嵌入式平台上的影像顯示、攝取、MPEG4 Codec等設備的Linux驅動程式,並自行撰寫影像硬體Linux驅動程式,作為軟硬體溝通的一個橋樑。
Recently, embedded SOC (system-on-a-chip) system is more complete and complex. It supports the integrated design of software and hardware for many applications. The technique of image object segmentation requires heavy computation so that it needs to be designed by software and hardware in SOC embedded system for real-time image surveillance system.
We develop techniques of image segmentation and background update based on ARM-based embedded SOC system. Although ARM processor is used widely in embedded system, it has slower speed than the personal computing processor. In order to achieve the real-time operation, we take the image processing with larger computing load to design as hardware accelerator. I implement the connected component labeling, color conversion and low-pass filter into hardware SIP (Silicon Intellectual Property). The interface of this SIP can fit for AMBA SOC interactions.
In the operating system environment, we modify the linux device driver to control the device of camera capture, image display and MPEG-4 Codec. In addition, I programmed a driver which can drive my hardware SIP in order to communicate between software and hardware.
中文摘要
Abstract
誌謝
目錄
表目錄
圖目錄
第一章、 Introduction
1.1 Motivations
1.2 The Purpose Statement
1.3 Organization of the Thesis
第二章、 Intelligent Video Surveillance System
2.1 Surveys of System Implementation
2.2 Image Object Segmentation Flow
2.3 Familiar Image Object Segmentation Method
2.4 Building and Updating Background
2.5 Stable Time Analysis
2.6 Background Model
2.7 The Situation of Still Object
2.8 Multi-Resolution and Variable Thresholding(MRVT)
2.9 Post Processing
第三章、 Fast Connected Components Labeling
3.1 Introduction
3.2 Fast Connected Components Labeling Method
3.2.1 Label Assigning
3.2.2 P1 – Process Element
3.2.3 P2 – Process Element
3.2.4 Pair Processing
3.3 Fast Connected Component Labeling Hardware Design
3.3.1 Label Assigning Hardware Architecture
3.3.2 Class Register Array Circuit
3.3.3 Combination Circuit
3.3.4 Fast Connected Components Labeling HW Architecture
3.4 Simulation Results
第四章、 Building SW& HW Environment for Embedded System
4.1 Introduction
4.2 LDK Evaluation Board Overview
4.3 Building Software Environment for LDK
4.3.1 Building and Burning Tool Chain
4.3.2 Building and Burning U-Boot
4.3.3 Building and Burning Linux Kernel
4.3.4 Building and Burning Root Filesystem
4.3.5 Building NFS Server and Client
4.3.6 Building Samba
4.3.5 Building CIFS
4.4 Building Multimedia Peripherals for LDK
4.4.5 Building Image Display : VGA Card
4.4.6 Building Image Display : CVBS interface Color LCD
4.4.8 Building Image Capture : IP Camera
4.4.9 Building MPEG-4 Codec
第五章、 Linux Device Driver
5.1 Introduction
5.2 Embedded Operating System
5.3 Linux Kernel
5.4 Linux Kernel Module
5.5 Char Drivers
5.5.1 Allocating and Freeing Device Numbers
5.5.2 Char Device Registration & Remove
5.5.3 System Calls
5.6 Polling and Interrupt
5.7 Waiting Queue
5.8 Driver Implementation
5.8.1 Introduction
5.8.2 VIP (Video Input Processor)
5.8.3 VOP (Video Output Processor)
5.8.4 MPEG-4 Codec
5.8.5 Connected Component Labeling SIP
第六章、 HW/SW Co-design for Object Segmentation
6.1 SOC (System-On-A-Chip)
6.2 AMBA On-Chip Bus
6.2.1 AHB Introduction
6.2.2 AHB Bus Interconnection
6.2.3 AHB Basic Transmission
6.2.4 AHB Control Signal
6.2.5 AHB Slave Response
6.2.6 AHB Arbitration
6.3 The Partition of Hardware/Software Co-design
6.4 System Profiling
6.5 The Interconnection between SOC and FPGA
6.6 The Performance Analysis of Hardware and Software
6.7 Object Segmentation System Integration and Application
第七章、 Conclusions and Future Work
7.1 Conclusions
7.2 Future Work
附 錄、
A. 1 LDK Basic Error Checking
A.2 VIP Control Registers Description
A.3 VOP Control Registers Description
A.4 MPEG-4 Encoder Control Registers Description
A.5 MPEG-4 Decoder Control Registers Description
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