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研究生:李振倫
研究生(外文):Chen-Lun Lee
論文名稱:多維圖樣變動長度之測試資料壓縮法
論文名稱(外文):Multi-Dimensional Pattern Run-Length for Test Data Compression
指導教授:曾王道
指導教授(外文):Wang-Dauh Tseng
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:27
中文關鍵詞:測試資料壓縮多維圖樣變動長度測試資料編碼系統單晶片自動測試機
外文關鍵詞:test data compressionpattern run-lengthcode-basedSOCATE
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由於超大型體電路技術的進步迅速,晶片的密度越來越高,使的晶片測試的難度也隨之上升,如龐大的測試資料、過長的測試時間、高功率的消耗和ATE (Automatic Test Equipment)的頻寬限制,皆造成測試成本的增加。為了要節省測試資料和測試時間,壓縮測試資料是一個常見且有效率的方法。本篇論文將利用run length code來表示test pattern的編碼資訊,來達成測試資料的壓縮。並採用多維空間的想法,來表達code的資訊。我們還會利用幾個方法來幫助壓縮,而這只需要幾個參數調整。而解壓縮非常簡單,不需要複雜的硬體架構。實驗結果將會說明此技術能提供高的壓縮率,來減少測試時間。
The density of integrated circuits increases as the result of the VLSI technology grows up. Hence, testing for integrated circuit is more and more complex. Such as the huge growth of the test time, high power consumption and bandwidth restriction of ATE (automatic test equipment) are lead to the increase in cost of testing. The proposed method presents a run-length-based compression method considering dimensions of pattern information. Information such as pattern length and number of pattern runs is encoded to denote the compression status. The decoder is simple and requires very low hardware overhead. Significant improvements are experimentally demonstrated on larger ISCAS’89 benchmarks.
1. INTRODUCTION - 1 -
2. PROPOSED METHOD - 4 -
2.1. MULTI-DIMENSIONAL PATTERN RUN-LENGTH COMPRESSION METHOD (MD-PRC) - 4 -
2.2. ONE-DIMENSIONAL PATTERN RUN-LENGTH COMPRESSION METHOD (1D-PRC) - 5 -
2.3. TWO-DIMENSIONAL PATTERN RUN-LENGTH COMPRESSION METHOD (2D-PRC) - 7 -
2.3.1. Control Code Length - 10 -
2.3.2. Minimum Pattern Length - 12 -
2.3.3. The compression flow for 2D-PRC - 13 -
2.4. 2.5-DIMENSIONAL PATTERN RUN-LENGTH (2.5D-PRC) COMPRESSION METHOD - 14 -
2.5. THREE-DIMENSIONAL PATTERN RUN-LENGTH (3D-PRC) COMPRESSION METHOD AND MORE - 15 -
3. MD-PRC DECODER DESIGN - 16 -
4. EXPERIMENTAL RESULTS - 20 -
5. CONCLUSION - 25 -
REFERENCES - 26 -
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[10]M. Tehranipoor, M. Nourani, and K. Chakrabarty, “Nine-Coded Compression Technique for Testing Embedded Cores in SoCs,” IEEE Trans. VLSI Systems, vol.13, no.6, pp.719-731, June 2005.
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