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研究生:鄭安深
研究生(外文):An-Shen Cheng
論文名稱:深度導向象限指派邏輯閘擺放演算法之研究
論文名稱(外文):A Study on Depth-driven Quadrant Dispatching Placement
指導教授:劉一宇
指導教授(外文):Yi-Yu Liu
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:50
中文關鍵詞:深度象限邏輯閘擺放
外文關鍵詞:depthquadrantplacement
相關次數:
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近年來由於半導體製程技術的進步,導線的delay已超過cell的delay,且cell的數目成長了好幾倍,導致複雜度也隨著攀升。所以在placement時,不但要考慮到wirelength,還要考慮到timing的問題。因此,我們提出了一個partition-based placement的演算法。為了能顧及timing與wirelength,我們依據depth大小來挑選要指派的cell。在指派cell時,我們依據面積與cell相鄰的關係來指派cell到適合的子象限。
實驗方面,我們與Capo、NTUplace3、SOC Encounter三個placement演算法做比較,並且比較各個演算法的WNS、TNS、wirelength、via使用個數與執行時間。在實驗結果方面,Capo、NTUplace3與SOC Encounter的平均WNS分別是我們演算法的58.74%、50.47%與60.08%。平均TNS分別是我們演算法的29.34%、27.14%與41.22%。平均wirelength分別是我們演算法的39.23%、41.05%與43.32%。平均via使用個數分別是我們演算法的80.97%、86.12%與87.79%。平均執行時間分別是我們演算法的17.12倍、1.63倍與5.15倍。
With the advance of semiconductor processing technology, wire delay dominates cell delay. Besides, the number of cells as well as the design complexity grows up rapidly in modern VLSI design. Hence, both the wirelength and timing problems must be carefully considered at placement stage. In this thesis, we propose a partition-based placement, which takes cell depth into account, to dispatch cells into a sub-quadrant recursively.
We compare three state-of-the-art placement tools, Capo, NTUplace3 and SOC Encounter. The experiment results of WNS, TNS, wirelength, via count, and runtime of all placement tools are reported. In average WNS, they are 58.74%, 50.47% and 60.08% better than ours. In average TNS, they are 29.34%, 27.14% and 41.22% better than ours. In average wirelength, they are 39.23%, 41.05% and 43.32% better than ours. In average via count, they are 80.97%, 86.12% and 87.79% better than ours. In average runtime, they are 17.12x、1.63x and 5.15x slower than ours.
摘 要...............................i
ABSTRACT...............................ii
誌 謝.............................iii
目 錄..............................iv
表 目 錄.......................vi
圖 目 錄.....................viii
一、簡介................................1
1.1 背景............................1
1.2 章節概述........................4
二、初步介紹............................5
2.1 預備知識........................5
2.1.1 Partition-based placement.......5
2.1.2 Analytical-based placement......6
2.2 觀察............................7
2.3 動機............................9
三、演算法.............................10
3.1 概觀...........................10
3.2 初始邏輯閘擺放.................12
3.3 邏輯閘面積平衡.................13
3.4 象限指派.......................14
3.5 相鄰指派.......................15
3.6 Pseudo-I/O加入.................16
3.7 Pseudo-I/O分離.................17
3.8 座標決定.......................18
四、實驗...............................22
4.1 實驗環境.......................22
4.2 實驗流程.......................22
4.3 實驗結果.......................24
五、總結與討論.........................29
5.1 總結...........................29
5.2 討論...........................29
5.3 未來工作.......................48
參 考 文 獻......................49
[1]Yih-Chih Chou and Youn-Long Lin, “Effective enforcement of path-delay constraints in performance-driven placement,” TCAD, VOL. 21, Issue 1, pp. 15–22, Jan. 2002.

[2]Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary and Bill Halpin, “Timing-driven force directed placement with physical net constraints,” ISPD, April 2003.

[3]Chanseok Hwang and M. Pedram, “Timing-driven placement based on monotone cell ordering constraints,” ASPDAC, pp. 201–206, Jan. 2006.

[4]A.E. Caldwell, A.B. Kahng and I,L. Markov, “Can recursive bisection alone produce routable placements?,” DAC, pp. 477–482, June 2000.

[5]Maogang Wang, Xiaojian Yang and M. Sarrafzadeh, “Dragon2000: standard-cell placement tool for large industry circuits,” ICCAD, pp. 260–263, Nov. 2000.

[6]Tung-Chieh Chen, Zhe-Wei Jiand, Tien-Chand Hsu, Hsin-Chen Chen and Yao-Wen Chang, “A high-quality mixed-size analytical placer considering preplaced blocks and density constraints,” ICCAD, pp. 187–192, Nov. 2006.

[7]N. Viswanathan and C. Chu, “FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model,” TCAD, VOL. 24, Issue 5, pp. 722–733, May 2005.

[8]N. Viswanathan, Pan Min and C. Chu, “Fastplace 2.0: an efficient analytical placer for mixed-mode designs,” ASPDAC, pp. 195–200, Jan. 2006.

[9]N. Viswanathan, Pan Min and C. Chu, “FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control,” ASPDAC, pp. 135–140, Jan. 2007.

[10]Opencores, http://www.opencores.org/.
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