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研究生:張世航
研究生(外文):Shih-Hang Chang
論文名稱:一個基於結構化客製晶片並用於可程式化鑽孔之繞線結構的繞線器
論文名稱(外文):A Router for Structured ASICs with Via Configurable Routing Fabric
指導教授:林榮彬林榮彬引用關係
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:英文
論文頁數:60
中文關鍵詞:繞線器可結構化客製晶片可程式化鑽孔之繞線結構
外文關鍵詞:RouterStructured ASICVia Configurable Routing Fabric
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可結構化客製晶片被使用來填補標準化客製晶片和FPGA之間的鴻溝。在過去,針對具有事先定義的繞線結構之可結構化客製晶片的繞線器並沒有受到應有之研究。在此篇論文中,我們針對可結構化客製晶片提出一個繞線器。我們的繞線器與其所用之繞線結構是互相獨立的。我們的繞線器主要分成以下幾個部分。一個用來把繞線結構轉換成繞線圖的繞線圖產生器。一個基於Dijkstra最短路徑演算法的multilevel routing。一個用於完成先前沒有完成繞線的rip-up和reroute的步驟。我們也設計一個語言去描述繞線結構。我們的繞線器整合至Synopsys和Cadence的標準化客製晶片工具來形成一個可結構化客製晶片之設計流程。實驗結果顯示,我們的繞線器可以100%完成ITC’99測試電路之繞線(最高到16900條線路和21100個邏輯閘)。就我們所知,我們是第一個學術研究團隊擁有此類之繞線器。之後,我們將針對大型電路去減少我們繞線器的執行時間。
Structured ASIC design methodology is invented to fill the gap between standard cell design and FPGA. Router for Structured ASIC designs with pre-defined routing fabric was not well investigated in the past. In this thesis, we proposed to develop a router for Structured ASICs. Our router is made to decouple from the underlying routing fabric. It has the following major components. A routing graph creater transforms routing fabrics into a routing graph. A multilevel routing approach based on Dijkstra shortest path algorithm that creates a route for each connection between two terminals. A rip-up and reroute procedure which completes the routing of nets that are not routed successfully in the previous step. As a by product, we also design a language to describe a routing fabric. Our router is integrated into a design flow based on Synopsys and Cadence tool sets for standard cell design. Extensive experiments performed for some of ITC’99 benchmarks show that our router can achieve 100% routing of these benchmarks (up to designs with 16900 nets and 21100 gates). To the best of our understanding, our router is the first of its kind done by an academic research group. In the future, we would like to reduce the run time required by our router for large designs.
List of Figures………………………………………………………………………x
List of Tables……………………………………………………………………….xiii
Chapter 1. Introduction………………………………………………………………1
1.1. Background………………………………………………………………...1
1.2. Scope of the Work and Contributions……………………………………...3
1.3. Thesis Organization………………………………………………………...3
Chapter 2. Related Work……………………………………………………………...4
2.1. Via Configurable Logic Blocks (VCLB)…………………………………...4
2.1.1. Via Configurations…………………………………………………..4
2.1.2. Combinational Cells………………………………………………....5
2.1.3. Sequential Cells……………………………………………………...5
2.1.4. Multi-Function Packed Blocks (MFPB)……………………………..6
2.1.5. Design Methodology………………………………………………....7
2.2. Routing Methodology with Routing Fabric…………………………………8
2.2.1. Routing Method of Standard Cell Routing…………………………...8
2.2.2. Routing Method of FPGA Routing…………………………………..9
2.2.3. Routing Method of Another Routing Flow………………………...11
2.3. Multilevel Routing…………………………………………………………13
2.4. Our Design Methodology…………………………………………………..15
Chapter 3. Routing Fabric Design……………………………………………………16
3.1. Language for Via Configurable Routing Fabric……………………………16
3.2. Via Configurable Routing Fabric…………………………………………..26
Chapter 4. Our Router………………………………………………………………..34
4.1. Routing Graph……………………………………………………………...34
4.1.1. Structure of Routing Graph……..…………………………………..34
4.1.2. Weight Assignment………...…………….………………………….36
4.2. Routing Algorithm………………………………………………………….40
4.2.1. Routing Graph With Used Vertices and Edges…..…...……………..41
4.2.2. Method for Choosing Pin Vertex and Steiner Vertex and Routing...43
4.3. Rip-Up and Reroute……………………………………………………..…47
Chapter 5. Experimental Results…………………………………………………….50
Chapter 6. Conclusions and Future Work…………………………………………….58
6.1. Conclusions………………………………………………………………...58
6.2. Future Work………………………………………………………………...58
References…………………………………………………………………………....59
[1] B. Zahiri, “Structured ASICs: Opportunities and Challenges,” ICCD, pp. 404-409,
2003.
[2] HardCopy ASIC Design Flow [Online]. Available: http://www.altera.com/products/software/flows/asic/qts-structured_asic.html
[3] eASIC: The configurable logic company [Online]. Available: http://www.easic.com
[4] Kun-Cheng Wu, Yu-Wen Tsai, “Structured ASIC, Evolution or Revolution?, “ ISPD, pp.103-106, 2004.
[5] L. Pileggi et al., “Exploring regular fabrics to optimize the performance-cost
trade-off, ” DAC, pp. 782-78, 2004.
[6] Zvi Or-bach, “Paradigm Shift in ASIC Technology In-stand Metal Out-stand Cell,” http://www.easic.com.
[7] Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin, “ Standard Cell Like Via-Configurable Logic Block for Structured ASICs, ” ISVLSI, pp. 381-386, 2008.
[8] Yajun Ran, Malgorzata Marek-Sadowska, “An Integrated Design Flow for a Via-Configurable Gate Array, ” ICCAD, pp. 582 – 589, 2004.
[9] Chetan Patel, Anthony Cozzie, Herman Schmit, Larry Pileggi, “An Architectural Exploration of Via Patterned Gate Arrays, ” ISPD, pp. 184 – 189, 2003.
[10] Vaughn Betz , Jonathan Rose, “VPR: A New Packing, Placement and Routing Tool for FPGA Research, ” FPL, pp. 213 – 222, 1997.
[11] V. Kheterpal, A. J. Strojwas, L. Pileggi, “Routing Architecture Exploration for Regular Fabrics, ” DAC, pp. 204 – 207, 2004.
[12] Monterey Design Systems [Online]. Available: http://www.montereydesign.com/
[13] Jason Cong, Jie Fang, Yan Zhang, “Multilevel approach to full-chip gridless routing, ” ICCAD, pp. 396 – 403, 2001.
[14] Jason Cong, Min Xie, Yan Zhang, “An enhanced multilevel routing system, ” ICCAD, pp. 51 – 58, 2002.
[15] K. Mikami, K. Tabuchi, “A computer program for optimal routing of printed circuit connectors,” IFIPs Proc, vol. H-47, pp.1475-1478, 1968.
[16] Yao-Wen Chang, Shih-Ping Lin, “MR: A New Framework for Multilevel Full-Chip Routing, ” TCAD, pp. 793 - 800, 2004.
[17] LEDA [Only]. Available: http://www.algorithmic-solutions.com/leda
[18] Dijkstra E W., “A note on two problems in connexion with graphs, ” In Numerische Mathematik, pp. 269 – 271, 1959.
[19] Cadence SOC Encounter [Online]. Available: http://www.cadence.com
[20] Antomn Guttman, “R-Trees: A Dynamic Index Structure for Spatial Searching, ” SIGMOD International Conference on Management of Data, pp. 47 – 57, 1984.
[21] Chris Chu, “FLUTE: Fast Lookup Table Based Wirelength Estimation Technique, ” ICCAD, pp. 696 – 701, 2004.
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