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研究生:吳新安
研究生(外文):Hsin-An Wu
論文名稱:以分割法加快漏電流消耗的估算
論文名稱(外文):A Partition-based Methodology for Simulation Acceleration of Leakage Power Estimation
指導教授:林榮彬林榮彬引用關係
指導教授(外文):Rung-Bin Lin
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:英文
論文頁數:47
中文關鍵詞:電路模擬漏電流
外文關鍵詞:simulationpartitioninginput vector controlleakage
相關次數:
  • 被引用被引用:0
  • 點閱點閱:246
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  • 下載下載:2
  • 收藏至我的研究室書目清單書目收藏:0
隨著半導體製程技術的進步,使得電路上的漏電流問題變得更為嚴重,造成許多不必要的功率消耗。然而當電路處於待命模式下,控制電路的輸入向量是一個有效降低漏電流的方法。但是在所有的輸入向量中要找出一個使電路進入較低功率消耗的向量是一個困難且耗時的工作,儘管如此、在有限的時間內透過電路模擬仍然是一個便利可行的方法。針對這個問題,我們提出一個快速估算電路漏電流的方法,經由這個方法可以快速找到電路最小漏電流的輸入向量。為了加速計算程序,首先我們將電路分割成數個較小的群以減少電路模擬所需的時間,然後再經由加總所有分割後電路的漏電流找出電路模擬過程中得到的最小漏電流的輸入向量。由實驗的結果證明在ISCAS及ITC99的電路,我們的方法和傳統的方法比較,應用在邏輯電路模擬可以得到平均三倍以上的加速,在某些電路上最快甚至可達十倍的加速。
Continuous decrease in feature size results in more transistors per area and more logic modules in a circuit. These changes in transistor density and integration scale of VLSI circuits make power consumption a more important and critical issue. Because of the transistor stacking effect, the leakage power of a logic gate depends on its input combination. Finding an input vector which leads a circuit into minimum leakage state is an active research area. Performing exhaustive simulation for all input vectors to find a minimum leakage vector (MVL) is not practical for large circuits because there are an exponential number of input vectors for a circuit. Despite of this, simulating a circuit using as many input vectors as possible to search for a MVL within a limited amount of time is still a handy and viable approach. In this thesis, we present a fast algorithm to reduce logic simulation time for finding an MVL of a circuit. In order to accelerate logic simulation, the circuit under simulation is partitioned into a set of sub-circuits first. All sub-circuits are pre-characterized for their leakage power with all possible input combinations. Total leakage power of the circuit can then be determined as the sum of individual sub-circuits. Experimental results show that simulation speedup is more than three times on average and up to ten times for some test circuits.
List of Figures vi
List of Tables vii
Chapter 1. Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Scope of the Work and Contributions 6
1.4 Thesis Organization 7
Chapter 2. Related Work 8
2.1 Components of Leakage Current 8
2.2 Modeling Different Leakage Components 9
2.2.1 Subthreshold Leakage Current 9
2.2.2 Gate Leakage Current 10
2.3 Total Leakage Current 11
2.4 Leakage Current in Transistor Stack 12
2.5 Input Vector Control for Leakage Reduction 13
2.5.1 Gate Replacement 13
2.5.2 Internal Point Control 14
2.5.3 Random Search Approach 14
2.5.4 Genetic Algorithm Approach 15
2.5.5 Divide-and-Conquer Approach 15
2.5.6 Fast Algorithm Approach 16
2.5.7 One-bit Random Algorithm 17
2.6 Directed Acyclic Graph 18
Chapter 3. Methodologies 21
3.1 Input Vector Control for Leakage Current 21
3.2 Leakage Current of a CMOS Logic Gate 22
3.3 Circuit Acyclic Clustering (CAC) with Input/Output Constraints 23
3.4 Gate-Level Simulator 28
Chapter 4. Experimental Results 31
Chapter 5. Conclusions 43
References 44
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