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研究生:李奕緯
研究生(外文):I-Wei Lee
論文名稱:一個基於結構化客製晶片並用於預先定義金屬層的時鐘繞線演算法
論文名稱(外文):A Clock Routing Algorithm for Structured ASIC with Predefined Metal Layers
指導教授:林榮彬林榮彬引用關係
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:52
中文關鍵詞:時鐘樹結構化客製晶片
外文關鍵詞:clock treestructured ASIC
相關次數:
  • 被引用被引用:0
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  • 下載下載:1
  • 收藏至我的研究室書目清單書目收藏:0
可結構化客製晶片被使用來填補標準化客製晶片和FPGA之間的鴻溝。過去有關於標準元件式的結構化客製晶片設計流程的研究並未專注在時鐘偏斜的議題。在這篇論文中,我們提出一個可結構化客製晶片的時鐘繞線演算法並使用預先定義的金屬線。我們的演算法以EZS演算法為基礎,在繞線的路徑上尋找存在於預先定義金屬線上的tapping point。 要使用預先定義好的金屬線,直接擴充EZS演算法,建構一個近似零偏斜的時鐘樹並不容易。因此,我們利用Dijkstra演算法,在預先定義的金屬線和可程式化的鑽孔所轉化成的圖中,尋找使用最少線總長的路徑來連結兩個pins或兩個tapping wires。另外,當連結兩個高度不平衡的子樹時,懸掛額外金屬線和使用蛇型路徑有助於我們尋找到tapping point。 實驗結果得知,對於每一個測試電路,我們的方法平均可以達成16毫奈秒。而線的總長,使用我們的方法是使用Cadence SOC Encounter的2.5倍到4倍。就我們所知,我們是第一個在使用預先定義的金屬線可結構化客製晶片建構近似零時鐘樹的研究。
Structured ASIC design methodology is invented to fill the gap between standard cell design and FPGA. Previous researches about standard cell like structured ASIC design do not focus on clock skew issue. In this thesis, we propose a clock routing algorithm for structured ASIC using predefined metal wires. Our algorithm based on exact zero skew (EZS) algorithm finds the tapping points on a routing path which consists of some predefined wires. A direct extension of EZS algorithm to construct a nearly zero skew clock tree using predefined metal wires is not a trivial task. Hence, we employ Dijkstra''s algorithm for connecting two pins or two tapping wires using the least wire length based on a graph model that represents the predefined metal wires and programmable vias. Hanging extra wires and wire snaking are employed to find a tapping point for a two highly unbalanced subtrees during merging. The experimental results show that our method can achieve a skew of 16 pico seconds on average for each circuit. However, the wire length of clock nets using our algorithm is 2.5 to 4 times of the wire length using Cadence SOC Encounter. To the best of our knowledge, this is the first work on constructing a near zero skew clock tree for a structured ASIC design with predefined metal wires.
List of Tables…………………………………………………………………………..x
List of Figures………………………………………………………………………...xi
Chaptre1 Introduction…………………………………………………………....1
1.1 Structured ASIC…………………………………………………………….1
1.2 Zero Skew Clock Routing…………………………………………………..3
1.3 Scope of the Work and Contributions………………………………………5
1.4 Thesis Organization…………………………………………………………6
Chaptre2 Related Work…………………………………………………………..7
2.1 Via Configurable Logic Blocks (VCLB)……………………………………7
2.2 Via Configurable Routing Fabric………………………………………….10
2.3 Exact Zero Skew (EZS) Algorithm………………………………………..13
Chaptre3 Clock Routing Algorithm for Structured ASIC with Predefined Metal Layers…………………………………………………………………...............16
3.1 Delay Calculation………………………………………………………….19
3.2 Graph Modeling…………………………………………………………...21
3.3 Tapping Wire and Tapping Point…………………………………………..22
3.4 Wire Snaking………………………………………………………………25
3.5 Wires Hanging……………………………………………………………..31
3.6 Entire Clock Net Routing Algorithm……………………………………...35
Chaptre4 Design Methodology………………………………………………....38
Chaptre5 Experimental Results…………………………………………………40
Chaptre6 Conclusions and Future Work……………………………………......49
6.1 Contributions………………………………………………………………49
6.2 Future Work………………………………………………………………..49
Reference……………………………………………………………………………..51
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