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研究生:黃一哲
研究生(外文):Yi-Che Huang
論文名稱:利用複製LUT之效能導向FPGA叢集演算法之研究
論文名稱(外文):LUT Duplication Performance-driven FPGA Clustering
指導教授:劉一宇
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:中文
論文頁數:35
中文關鍵詞:叢集
外文關鍵詞:FPGAclusteringmapping
相關次數:
  • 被引用被引用:0
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  • 下載下載:7
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在傳統的FPGA設計流程中,clustering對於FPGA晶片的效能和面積這兩個部分影響極大。因為FPGA設計流程中,technology mapping和clustering這兩個程序是彼此分開考量, clustering需要technology mapping做完後的電路,但是其電路會影響到clustering後的結果。針對這個問題,我們提出利用複製LUT的方式來調整原本的電路,進而有利於clustering的演算法,進而可以降低delay。在實驗方面,則和DAOmap + T-VPack這兩個technology mapping和clustering的演算法相做比較,最後由實驗數據比較後,我們的演算法在效能方面比DAOmap + T-VPack增加了14.6%,而面積只多了3%。
Island-style FPGA is one of a well-known pre-fabricated design styles with very high design flexibility. In a conventional FPGA design flow, circuits are mapped and clustered into configurable logic blocks (CLB) before being placed and routed. Hence, technology mapping and clustering result in great performance and area impacts in synthesis level. Since the delay models used for both two steps are different, optimizing a design in the two separated steps fails to obtain good final circuit. In this thesis, we propose a two-step method to optimize the clustering procedure. We duplicate the lookup tables (LUTs) in pre-clustering step to remove potential external interconnect between CLBs. Furthermore, we duplicate a predecessor LUT of a flip-flop once when the LUT has multiple fanouts to reduce the circuit levels with no area overheads. The experimental results demonstrate that our proposed method is capable of improving the circuit performance by 14.6% with only 3% area overheads as compared with the conventional FPGA design flow.
目錄
摘要····················································· i
ABSTRACT·················································ii
誌謝··················································· iii
表目錄·················································· vi
圖目錄················································· vii
一、 緒論················································ 1
1.1 前言················································· 1
1.2 章節概述············································· 2
二、 相關研究············································ 3
2.1 預備知識············································· 3
2.1.1 FPGA 之架構········································ 3
2.1.2 FPGA Design Flow··································· 6
2.2 DAOmap··············································· 8
2.2.2 DAOmap 演算法······································ 8
2.3 T-VPack ·············································11
2.3.1 定義···············································11
2.3.2 T-VPack 演算法···································· 12
2.4 Simultaneous Mapping and Clustering (SMAC)·········· 13
2.4.1 定義···············································14
2.4.2 SMAC 之演算法······································15
三、 問題描述與演算法··································· 17
3.1 問題描述與定義·······································17
3.2 演算法···············································18
3.2.1 Pre-clustering ····································19
3.2.2 LUT duplication 和De-clustering··················· 21
3.2.3 整合LUT 和flip-flop······························· 22
3.2.4 Clustering ········································23
四、 實驗與實驗結果····································· 25
4.1 實驗環境············································ 25
4.2 實驗流程············································ 25
4.3 實驗結果············································ 26
五、 結論··············································· 32
參考文獻················································ 33
[1]D. Chen and J. Cong, “DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs,”In Proceedings of IEEE/ACM international conference on Computer-aided design(ICCAD), Nov. 2004.

[2]Joey Y. Lin, D. Chen, and J. Cong, “Optimal Simultaneous Mapping and Clustering for FPGA Delay Optimization,” In Proceedings of IEEE/ACM Design Automation Conf.(DAC), 2006.

[3]A. Marquardt, V. Betz and J. Rose, “Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density,” In Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1999, pp. 37 - 46.

[4]V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, February 1999.

[5]R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Improved Logic Synthesis Algorithms for Table Look Up Architectures,” In Proceedings of IEEE/ACM international conference on Computer-aided design(ICCAD), Nov. 1991.

[6]R. Francis, J. Rose, and Z. Vranesic, “Chortle-crf: Fast Technology Mapping for Lookup Table-based FPGAs,” In Proceedings of IEEE/ACM Design Automation Conf.(DAC), 1991.

[7]J. Cong and Y. Ding, “FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,”In IEEE Transaction on CAD, Vol.13, No.1, Jan. 1994

[8]K. C. Chen, J. Cong, Y. Ding, and P. Trajmar, “DAG-Map: Graph-based FPGA Technology Mapping for Delay Optimization,”In IEEE Design and Test of Computers, vol. 9, no. 3, pp. 7-20, Sep., 1992.

[9]J. Cong and Y. Hwang, “Simultaneous Depth and Area Minimization in LUT-Based FPGA Mapping,” In Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 1995.

[10]A. Mishchenko, S. Chatterjee, and R. Brayton, “Improvements to Technology Mapping for LUT-Based FPGAs,” In Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2006.

[11]T. takata, and Y. Matsunaga, “Area Recovery under Depth Constraint by Cut Substitution for Technology Mapping for LUT-based FPGAs,” In Proceedings of IEEE/ACM ASPDAC, 2008.

[12]V. Manohararajah, S. D. Brown, and Z. G. Vranesic, “Heuristics for Area Minimization in LUT-Based FPGA Tecnology Mapping,” In Proceedings of the International Workshop on Logic and Synthesis, Temecula, California, USA, June 2004, pp. 14-21.

[13]D. Chen, J. Cong, and P. Pan, FPGA Design Automation: A Survey, Foundations and Trends in Electronic Design Automation, Vol. 1, No 3, pp.195-330, November 2006.
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