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研究生:陳信宇
研究生(外文):Sin-Yu Chen
論文名稱:一個結構化客製晶片的電源閘設計方法
論文名稱(外文):A Power Gating Design Methodology for Structured ASIC
指導教授:林榮彬林榮彬引用關係
指導教授(外文):Roung-Bin Lin
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:40
中文關鍵詞:電源閘低洩漏功率結構化客製晶片標準函式庫基本單元
外文關鍵詞:power-gatinglow leakage powerstructured ASICstandard cell librarycell library
相關次數:
  • 被引用被引用:0
  • 點閱點閱:130
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  • 下載下載:3
  • 收藏至我的研究室書目清單書目收藏:0
積體電路(IC)的製程越來越先進,在設計IC時要處理的問題也越來越困難。一般來說,一個晶片是由多的金屬層組成,但在越先進的製程中,製作金屬層的光罩費用變得相當龐大。為了在IC設計的成本和效能間取得平衡,因此出現一個新的設計方法,稱作結構化客製晶片。結構化客製晶片是由一些預製的電晶體、事先定義完成的金屬層,和尚未定義的鑽孔(via)層(或少許金屬層)組成。設計者僅需製作少量光罩來完成設計且可平分預製的光罩費用來降低成本。除此之外,越小製程中邏輯元件的洩漏功耗已成一個重大問題。為了降低洩漏功耗,已有許多方法被提出,當中電源閘技術為一個有效的方法,此技術是截斷停滯的邏輯區塊的供應電源來降低洩漏功率。在此篇論文中,我們提出一個將結構化客製晶片結合電源閘技術的設計方法。以我們的基本單元設計的電路在時間延遲上可達到用一般結構化客製晶片函式庫的0.48倍的洩漏功率而只多出1.16倍的延遲和1.07倍的晶片面積。
With the advances in integrated circuit(IC) process, IC design issues that need to be handled will be more difficult. Since a chip consists of numerous pattern formational layers, mask cost becomes very large for an advanced manufacturing process. To reduce the cost of IC design and manufacturing, structured ASIC emerges as a new design alternative. Structured ASIC consists of some prefabricated transistors and prefabricated masks for some metal layers, and a couple of un-customized mask layers for vias. The designers need only to customize a few masks to complete the design, and share the cost of prefabricated masks. As technology scales, leakage power consumption becomes a serious problem. Among the leakage power reduction methods, power gating is a commonly used technique that disconnects idle blocks from the power network. In this thesis, we design a via-configurable logic block (VCLB) that enables power gating designs and propose a structured ASIC design methodology based on power-gated VCLB. Experimental results show that the leakage power of the designs is on average 0.48 times that of the designs without using power-gating at the expense of 1.16 times delay and 1.07 times area.
List of Figures iii
List of Tables iv
Chapter 1. Introduction 1
1.1. Background 1
1.2. Scope of the Work 3
1.3. Thesis Organization 3
Chapter 2. Related Works 5
2.1. Structured ASICs 5
2.2. Power-Gating Design 8
Chapter 3. Implementation 11
3.1. Separating-style Design 11
3.1.1. VCLB Design 11
3.1.2. Sleep Transistor Design 13
3.1.3. Methodology and Problems 14
3.1.4. Timing Analysis for Separating-style Design 16
3.2. Combining-style Design 18
3.2.1. Power-gating VCLB design 18
3.2.2. Configurability of Power-Gated VCLB 20
Chapter 4. Methodology 22
4.1. Cell Library Creation 23
4.2. Chip Design Flow 24
4.3. Sleep Transistor Sizing 24
Chapter 5. Experimental Results 26
Chapter 6. Conclusions 37
References 38
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