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研究生:游濟維
研究生(外文):Chi-Wei Yu
論文名稱:決定式內嵌式自我測試架構下藉由多重線性回饋移位暫存器達到低功率測試
論文名稱(外文):Deterministic Built-in Self-Test Using Multiple LinearFeedback Shift Registers for Low-Power Scan Testing
指導教授:曾王道
指導教授(外文):Wang-Dauh Tseng
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:19
中文關鍵詞:決定式內嵌式自我測試線性回饋移位暫存器低功率測試
外文關鍵詞:DeterministicBuilt-in Self-TestBISTLinear Feedback Shift RegisterLFSRLow-Power Scan Testing
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  • 被引用被引用:0
  • 點閱點閱:127
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  • 下載下載:1
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在現今的VLSI測試中有兩個重大的挑戰,第一是過大的測試資料量,第二是在測試過程中過多的功率消耗。本篇論文提出了一個在內嵌式自我測試(BIST)架構下減少功率消耗。一開始利用minimum transition filling (MTF)的方法來產生低功率的測試資料,接著再將低功率的測試資料利用Neighboring Bit-wise Exclusive-OR (NB-XOR) Transform的技術轉換得到有助於壓縮的測試資料模型。並且在決定式內嵌式自我測試架構下藉由多重線性回饋移位暫存器產生測試資料來達到減少測試資料的效果。實驗結果顯示,在ISCAS’89的測試資料中利用提出的方法不僅可以明顯的減少功率的消耗還可以達到不錯的壓縮效果。
Large test data volume and excessive testing power are two strict challenges for today’s VLSI testing. This thesis presents a BIST-based method for reducing testing power. A low power test set is first determined through the application of minimum transition filling (MTF) on the test cubes. The technique of Neighboring Bit-wise Exclusive-OR (NB-XOR) Transform is applied to pre-process the test data to help improve the compression effect. A BIST-based scheme using multiple LFSRs is then constructed to compress test data and generate the target test set. Experimental results show, this method can reduce the shift-in power significantly and also has good compression effect for larger ISCAS’89 benchmark circuits.
1. INTRODUCTION 1
2. PROPOSED METHOD 4
2.1 MTF TRANSFORM 5
2.2 MULTIPLE LFSRS COMPRESSION 6
2.2.1 NB-XOR Transform 6
2.2.2 Test Data Generation by Multiple LFSRs 7
2.3 NB-XOR DECOMPRESSION 10
3. PROPOSED ARCHITECTURE AND METHOD FLOW 11
4. EXPERIMENTAL RESULT 13
5. CONCLUSION 17
6. REFERENCE 18
[1] J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Embedded deterministic test”, IEEE Trans. CAD, May 2004, vol. 23, pp. 776-792.

[2] S. Mitra and K. S. Kim, “X-Compact., “An efficient response compaction technique”, IEEE Trans. CAD, Mar. 2004, vol. 23, pp. 421-432.

[3] B. Koenemann, C. Banhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater, “A SmartBIST variant with guaranteed encoding”, in Proc. Asia Test Symp., 2001, pp. 325-330.

[4] S. Mitra and K. S. Kim, “XMAX: X-Tolerant architecture for maximal test compression”, in Proc. IEEE Intl. Conf. Computer Design, 2003, pp. 326-330.

[5] B. Koenemann, “LFSR-coded test pattern for scan designs”, in Proc. Eur. Test Conf., Munich, Germany, Apr. 1991, pp. 237–242

[6] G. Jervan, P. Eles, Z. Peng, R. Ubar, and M. Jenihhin, “Test Time Minimization for Hybrid BIST of Core-Based Systems”, J. Comput. Sci. Tech., vol. 21, Nov. 2006, pp.907-912.

[7] S. Hellebrand, H. Linag and H.-J. Wunderlich, “A mixed-mode BIST scheme based on reseeding of folding counters”, in Proc. Int. Test Conf., 2000, pp. 778-784.

[8] C. Krishna, A. Jas and N.A. Touba, “Test vector encoding using partial LFSR reseeding”, in Proc. Int. Test Conf., 2001, pp. 885-89s3.

[9] S. Wang, “Low hardware overhead scan based 3-weight weighted random BIST”, in Proc. Int. Test Conf., 2001, pp. 868-877.

[10] W.-D. Tseng, “Scan chain ordering technique for switching activity reduction during scan test,” in Proc. IEE Comput. Digit. Tech., vol. 152, no.5, 2005, pp 609-617.

[11] J. Li, Y. Han, and X. Li, “Deterministic and low power BIST based on scan slicing overlapping”, IEEE Int. Symp. Circuits. Syst., May 2005, vol. 6, pp. 5670–5673.

[12] J. Lee, N. A. Touba, “LFSR-reseeding scheme achieving low power dissipation during test”, IEEE Trans. CAD, Feb 2007, vol. 26, no. 2, pp. 396–401.

[13] P. Rosinger, B.M. Al-Hashimi, and N. Nicolici, “Dual multiple polynomial LFSR for low-power mixed-mode BIST”, in Proc. IEE Comput. Digit. Tech., vol. 150, no. 4, pp. 209-217, Jul. 2003.

[14] M.-H. Yang, Y. Kim, Y. Park, D. Lee, and S. Kang, “Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing,” IET Comput. Digit. Tech., vol. 1, no. 4, pp. 369–376, July 2007.

[15] R. Sankaralingam, R. R. Oruganti, and N. A. Touba, “Static compaction techniques to control scan vector power dissipation,” in Proc. IEEE VLSI Test Symp., 2000, pp. 35-40.

[16] J. Song, H. Yi, D. Hwang, and S. Park, “A Compression Improvement Technique for Low-Power Scan Test Data,” in Proc. TENCON, Nov. 2006, pp. 1-4.
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