臺灣博碩士論文加值系統

在現今的VLSI測試中有兩個重大的挑戰，第一是過大的測試資料量，第二是在測試過程中過多的功率消耗。本篇論文提出了一個在內嵌式自我測試(BIST)架構下減少功率消耗。一開始利用minimum transition filling (MTF)的方法來產生低功率的測試資料，接著再將低功率的測試資料利用Neighboring Bit-wise Exclusive-OR (NB-XOR) Transform的技術轉換得到有助於壓縮的測試資料模型。並且在決定式內嵌式自我測試架構下藉由多重線性回饋移位暫存器產生測試資料來達到減少測試資料的效果。實驗結果顯示，在ISCAS’89的測試資料中利用提出的方法不僅可以明顯的減少功率的消耗還可以達到不錯的壓縮效果。

Large test data volume and excessive testing power are two strict challenges for today’s VLSI testing. This thesis presents a BIST-based method for reducing testing power. A low power test set is first determined through the application of minimum transition filling (MTF) on the test cubes. The technique of Neighboring Bit-wise Exclusive-OR (NB-XOR) Transform is applied to pre-process the test data to help improve the compression effect. A BIST-based scheme using multiple LFSRs is then constructed to compress test data and generate the target test set. Experimental results show, this method can reduce the shift-in power significantly and also has good compression effect for larger ISCAS’89 benchmark circuits.

1. INTRODUCTION 1
2. PROPOSED METHOD 4
2.1 MTF TRANSFORM 5
2.2 MULTIPLE LFSRS COMPRESSION 6
2.2.1 NB-XOR Transform 6
2.2.2 Test Data Generation by Multiple LFSRs 7
2.3 NB-XOR DECOMPRESSION 10
3. PROPOSED ARCHITECTURE AND METHOD FLOW 11
4. EXPERIMENTAL RESULT 13
5. CONCLUSION 17
6. REFERENCE 18

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