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研究生:蔡賜錡
研究生(外文):Tsu-Chi Tsai
論文名稱:使用固定樣式運轉編碼之測試資料壓縮
論文名稱(外文):Test Data Compression Using Fixed Pattern Run-Length Coding
指導教授:曾王道
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:41
中文關鍵詞:固定樣式資料壓縮
外文關鍵詞:PatternRun-Length
相關次數:
  • 被引用被引用:0
  • 點閱點閱:124
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  • 下載下載:1
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文中,提出了一個簡單的Encode scheme 來壓縮測試資料,我們將輸入的測試資料分割為segment, 藉由檢查segment特性,將其分為不同的類型,再用對應的編碼方式編碼以減少測試資料量,壓縮過後的測試資料,會經由一個架構簡單的decoder解碼回原本的segment,再送進電路做測試,此架構所額外附加的硬體對原本電路沒有任何影響,為decoder和一個buffer,所以硬體方面的額外成本並不高,並且獨立於測試電路,因此可應用在多種電路上,而且在稍加修改後,也可以在multiple scan chain架構下使用,編碼方式和decoder完全相同,因此具有較為廣泛的實用性,在原本架構下對於ISCAS89’電路的實驗結果平均可達到65.2847%,而在multiple scan chain的架構下,也可以達到63.9948%的壓縮率,不論在哪種架構下都有不錯的效果。
We present a compression method with simple encoding scheme and hardware architecture. Partitioning the test data ion segments, and then checking the characteristic of each segment. Finally compressing data according to encoding table. The compressed data is restored by a decoder with simple architecture to be shifted in CUT(circuit under test).There is no any modifying with original circuit. Only a decoder and a buffer have to be added, so the extra hardware cost is lower. Because the method is independent from CUT, so it can combine with many type of circuit. It even can be used on multiple scan chain by a little modifying, and the modifying does not change the encoding scheme and decoder. The average compression result can reach 65.28% with circuit in ISCAS89'', and 63.99 on multiple scan chain.
1. INTRODUCTION 1
2.RELATED WORK 2
3.COMPRESSION SCHEME 9
4.HARDWARE ARCHITECTURE AND IMPORVE 14
4.1 HARDWARE ARCHITECTURE OF DECODER 14
4.2.IMPORVE METHOD 20
6. CONCLUSION 28
7. REFERENCES 29
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[7]A. Jas, J. Ghosh-Dastidar, Ng, and N. A. Touba, “An efficient test vector compression scheme using selective huffman coding,” IEEE Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 6, pp. 797–806, Jun. 2003

[8]M. H. Tehranipour, M. Nourani, and K. Chakrabarty, “Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression,” in Proc. DATE, 2004, pp.1284–1289.



[9]M. Nourani and M. Tehranipour, “RL-Huffman encoding for test compression and power reduction in scan applications,” in Proc. IEEE TODAES,2005, pp. 91–115.
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[11]S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois,“Built-in test for circuits with scan based on reseeding of multiple polynomial linear feedback shift registers,” IEEE Trans. Computers, vol. 44, no. 2, pp. 223–233, Feb. 1995.

[12]C. Krishna and N. A. Touba, “Reducing test data volume using LFSR reseeding with seed compression,” in Proc. Int. Test Conf., 2002.

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[15]S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R. Kapur, and T. W.Williams, “A reconfigurable shared scan-in architecture,” in Proc. IEEE VLSI Test Symp., 2003, pp. 9–14.

[16]I. Bayraktaroglu and A. Orailoglu, “Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression,” in Proc. IEEE VLSI Test Symp., 2003, pp. 113–118.

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[21]Flottes, M.-L. Poirier, R. Rouzeyre, B. “An arithmetic structure for test data horizontal compression.” Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings Volume 1, 16-20 Feb. 2004 Page(s):428 - 433 Vol.1

[22]Jinkyu Lee, Touba, N.A. “Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition.” Test Symposium, 2006. ATS ''06. 15th Asian 20-23 Nov. 2006 Page(s):237 – 244

[23]Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen-Ching Wu. “A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.” IEEE Trans. on VLSI Syst., Volume 15, Issue 7, July 2007 Page(s):767 – 776

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