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研究生:羅彥翔
研究生(外文):Yan-Xiang Luo
論文名稱:蕭特基快閃記憶體之設計與模擬
論文名稱(外文):Design and Simulation of Schottky Barrier Flash Memory
指導教授:施君興
學位類別:碩士
校院名稱:元智大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
中文關鍵詞:蕭特基能障快閃記憶體熱電子
外文關鍵詞:Schottky BarrierFlash MemoryHot Electron
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浮動閘式快閃記憶體近年來已為主流的非揮發性半導體記憶體,但在元件尺寸微縮下,遇到使用偏壓過高與熱電子寫入效率不佳等問題。本文利用二維元件模擬,探討新式蕭特基能障快閃記憶體的寫入特性,並研究各種元件架構對其寫入特性之影響。蕭特基能障快閃記憶體因在源極/通道介面上具有蕭特基能障之特點,有別於傳統的浮動閘式元件,其具備源極端熱電子注入之寫入特性,可加強熱電子效應並在較低的操作偏壓下,提高寫入的閘極電流。另一方面,使用雙功函數閘極、摻雜分離層以及SOI(Silicon-On-Insulator)基板,亦能進一步的提高寫入時的閘極電流,有效解決使用偏壓過高與熱電子寫入效率不佳等問題。
The standard floating gate Flash cells is the mainstream nonvolatile semiconductor memory. The challenges to future scaling are imposed by the non-scalable tunneling oxide and high voltage to provide sufficient drain-side hot electron injections. This study uses two-dimensional device simulator to present a novel Schottky barrier source/drain Flash memory cell with promising source-side hot electron injection. Rather than conventional cell, the unique Schottky barrier formed at source/channel interface significantly promotes the amount of source-side hot electrons to provide high injection efficiency at considerably low voltages without compromising between gate and drain biases. An optimal design of Schottky Barrier Flash cell is achieved using the dopant segregation layer, silicon-on-insulator substrate and dual workfunction gate with enhanced gate current.
中文摘 要 III
英文摘要 IV
目錄 V
圖目錄 VII
表目錄 X
第一章 序論
1.1 記憶體簡介 1
1.2 研究動機與目標 2
1.3 論文結構 3
第二章 浮動閘式快閃記憶體元件
2.1 操作原理 5
2.2 寫入機制-熱電子注入 8
2.3 抹除機制-福勒諾漢穿遂 10
2.4 元件設計上的限制 11
第三章 蕭特基能障元件
3.1 蕭特基接觸 12
3.2 歐姆接觸 15
3.3 蕭特基能障金氧半場效應電晶體 16
3.4 蕭特基能障快閃記憶體元件 20

第四章 蕭特基能障快閃記憶體元件寫入特性
4.1 模擬工具與物理模型 22
4.2 寫入特性 23
4.3 元件尺寸微縮對寫入特性影響 30
4.4 結果與討論 31
第五章 蕭特基能障快閃記憶體元件設計
5.1 汲/源極工程-摻雜分離層 32
5.2 基板工程-絕緣體基板( Silicon – On – Insulator )   39
5.3 閘極工程-雙功函數閘極            42
第六章 結論
參考文 獻 47
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