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研究生:王志誠
研究生(外文):Chih-Cheng Wang
論文名稱:使用變壓器架構之24GHzCMOS功率放大器
論文名稱(外文):24 GHz Transformer Based CMOS Power Amplifier
指導教授:黃建彰黃建彰引用關係
學位類別:碩士
校院名稱:元智大學
系所名稱:通訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:90
中文關鍵詞:CMOS功率放大器k-bamd
外文關鍵詞:CMOSPower Aplifierk-band
相關次數:
  • 被引用被引用:2
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  • 下載下載:8
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本論文主要針對24-GHz 微波CMOS 功率放大器之研究設計,晶片製作使用國家晶片中心提供的標準TSMC CMOS 0.18 μm製程,內容包括研究毫米波單晶變壓器(Millimeter Wave Monolithic Transformers)及功率放大器(Power Amplifiers)的設計。首先專注於研究單晶變壓器,並且提出了功率結合及阻抗轉換的觀念來達到高功率輸出。此外,提出利用單晶微波及毫米波積體電路(Monolithic Microwave / Millimeter Wave Integrated Circuits, MMICs)技術所設計的功率放大器,分別設計在K 頻帶(24-GHz),。電路採全積體化方式使用標準TSMC CMOS 0.18 μm製程製作完成,其模擬得到的功率輸出有20dBm,增益為16 dB,PAE約15%;而以目前CMOS製程技術,操作在此頻段下之功率放大器仍未有高達20dBm之研究。量測得到的功率輸出有16.4dBm,增益為6 dB,PAE約5%。最後探討實驗結果與模擬誤差原因及改進方式。
This thesis presents a 24 GHz full-integrated power amplifier (PA) which designed and fabricated in the 0.18-μm 1P6M standard CMOS technology. This power amplifier is a 2-stage design using cascode configuration with the broadside transformers. The simulation shows the PA achieves the maximum output power of 20.3 dBm and OP1dB of 16.45 dBm, a power added efficiency (PAE) of 15.3%, and a linear gain of 16.5 dB when VDD is biased at 3.0 V. The measured results shows the maximum output power of 16.4 dBm and OP1dB of 12.68 dBm, a power added efficiency (PAE) of 5.3%, and a linear gain of 5.6 dB when VDD is biased at 3.0 V. The chip size is only 0.59 x 0.47 mm2.
Finally, the differences between simulations and measurement results are addressed with some possible improvement directions.
目 錄

書名頁...............................................i
論文口試委員審定書...................................ii
授權書...............................................iii
中文摘要.............................................iv
英文摘要.............................................v
誌謝.................................................vi
目錄.................................................vii
表目錄...............................................ix
圖目錄...............................................x

第一章 緒論.........................................1
1.1 研究背景........................................1
1.2 研究動機........................................2
1.3 章節概述........................................3

第二章 功率放大器基本理論...........................5
2.1 簡介............................................5
2.2 功率放大器特性..................................5
2.2.1 功率放大器主要規格簡介..................6
2.2.2 功率放大器非線性特性....................9
2.3 功率放大器種類..................................13
2.3.1 線性式功率放大器........................17
2.3.2 開關式功率放大器........................20
2.4 負載線設計法....................................21
2.4.1 共軛匹配與功率匹配......................21
2.4.2 Cripps負載線理論........................24
2.4.3 Load-pull與Source-pull系統..............30

第三章 應用於RFIC射頻晶片變壓器.....................33
3.1 簡介............................................33
3.2 被動元件與IC設計................................33
3.3 變壓器之原理....................................35
3.4 變壓器的參數與架構..............................36
3.5 變壓器之等效模型................................41
3.6 變壓器特性指標..................................45
3.7 變壓器範例......................................48
3.7 變壓器設計流程..................................61

第四章 使用變壓器架構24 GHz CMOS功率放大器之設計....62
4.1 簡介............................................62
4.2 CMOS功率放大器..................................63
4.2.1 元件挑選....................................63
4.2.2 直流分析....................................64
4.2.3 交流分析....................................66
4.2.4 使用Load-pull系統找出最佳阻抗點.............68
4.3 Broadside變壓器之設計...........................69
4.4 電路模擬與量測結果..............................76

第五章 結論.........................................82

VITA.................................................86

參考文獻.............................................87
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[12]Chung-Yu Wu, Shun-Wei Hsu, and Wen-Chieh Wang, “A 24-GHz CMOS Current-Mode Power Amplifier with High PAE and Output Power,” Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, May 2007, pp.2866 – 2869
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