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研究生:林侑融
研究生(外文):You-Rong Lin
論文名稱:應用於軟體無線電架構之正交分頻多工系統與波束成型器基頻電路設計
論文名稱(外文):Design of Base-band Circuits for OFDM System and Beamformer Based on SDR Structure
指導教授:馬杰馬杰引用關係
指導教授(外文):Jeich Mar
學位類別:博士
校院名稱:元智大學
系所名稱:通訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:128
中文關鍵詞:軟體無線電正交分頻多工數位波束成型通道模擬器超寬頻
外文關鍵詞:software defined radio (SDR)orthogonal frequency division multiplexing (OFDM)digital beamforming (DBF)channel simulatorUltra Wide Band (UWB)
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本論文研究軟體無線電(Software Defined Radio, SDR)架構之正交分頻多工(Orthogonal Frequency Division Multiplexing, OFDM)無線通訊系統與智慧型天線之基頻電路,主要研究項目分成四大部分。在第二章提出一建構於時域的插補器(interpolator)與縮減器(decimator)構架,用來實現五位元128音(128-tone) Sigma-Delta調變(SDM)之數位類比轉換器與類比數位轉換器,可以減少UWB OFDM系統的量化雜訊與功率消耗。在第三章提出一軟體無線電通道模擬器架構及重新配置可程式邏輯閘(field programmable gate array, FPGA)硬體處理模組之方法。藉由軟體重新配置硬體的方式,在不需要修改其硬體的前提下,提供使用者按其需求產生不同無線通訊系統衰減通道之功能,並可依使用者需求,增加不同無線通訊系統發射波形與衰減通道軟體碼可被用於測試多種不同無線通訊系統之傳收機。在第四章提出一建構於軟體無線電架構之多模式數位波束成型器,應用在微衛星(micro-satellite)合成孔徑雷達(Synthetic Aperture Radar, SAR),可以減少酬載空間,並有效率地減少功率消耗。在第五章提出一建構於軟體無線電架構之主動相列雷達系統,以16-QAM與64-QAM多載波直接序列展頻(Multi-Carrier Direct Sequence Spread Spectrum, MC-DSSS)波形量測目標距離與速度,並且在FPGA實現MC-DSSS基頻接收機與快速傅立葉轉換之多模式數位波束成型器,驗證目標來向(direction of arrival, DOA)量測與消除干擾信號之硬體重新配置功能。
Based on software defined radio (SDR) structure, the baseband circuits of the orthogonal frequency division multiplexing (OFDM) system and smart an-tenna are designed in the dissertation. It includes four major research items. In chapter 2, for the purpose of reducing the quantization noise and power con-sumption of UWB-OFDM transceiver, a new time domain-based interpolator and decimator structure is proposed to realize five-bit 128-tone sigma-delta modulation (SDM) D/A and A/D converters. In chapter 3, a SDR channel simulator is designed for testing the base band transceiver of various wireless communication systems. The proposed SDR architecture and the hardware re-configuration scheme are used to reconfigure the processing modules when the channel conditions are changed. In chapter 4, the hardware reconfiguration feature of a SDR architecture can support multiple modes of digital beam-former (DBF) striving for compactness and efficient processing power, which are the important issues for the micro-satellite SAR systems. In chapter 5, based on the SDR structure, an active phased array radar system consisting of the 16-QAM and 64-QAM multi-carrier direct sequence spread spectrum (MC-DSSS) waveforms for target range and velocity measurement is pro-posed. In addition, the radar baseband receiver and the FFT-based multi-mode DBF are realized in the field programmable gate array (FPGA) for the target DOA measurement and jamming cancellation to demonstrate the function of the hardware reconfiguration.
摘要 i
Abstract ii
Acknowledgement iii
Contents iv
List of Tables vii
List of Figures viii
Mathematical Notation xi
Abbreviations xiii
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.1.1 Data Converter for SDR systems 2
1.1.2 Channel Simulator for SDR Systems 2
1.1.3 SDR Phased Array Radar Systems 3
1.2 Organization of the Dissertation 5
Chapter 2 A New Five-bit 128-tone Sigma-Delta Modulation D/A and A/D Converters for UWB-OFDM Transceiver 8
2.1 Introduction 8
2.2 Time Domain-Based Interpolation and Decimation for N-tone SDM UWB-OFDM Transceiver 12
2.2.1 One-bit N-tone SDM UWB-OFDM Transceiver 12
2.2.2 Time Domain-Based Interpolation and Decimation 17
2.2.3 Optimal Quantization Size 21
2.3 Using Time Domain-Based Interpolation/Decimation to Implement Time-Domain Spread/De-spread Processing 23
2.4 Five-Bit 128-Tone SDM A/D Converter 27
2.5 Simulations and Numerical Evaluations 34
2.6 Summary 43
Appendix 2 44
Appendix 2.A Derivation of (2.11) 44
Appendix 2.B Derivation of (2.20) 45
Appendix 2.C Derivation of (2.26) 45
Appendix 2.D Derivation of (2.31) 46
Chapter 3 Design of Software Defined Radio Channel Simulator for Wireless Communications: Case Study with DSRC and UWB Channels 48
3.1 Introduction 48
3.2 Channel Algorithms for DSRC and UWB Systems 50
3.3 SDR Architecture and Reconfiguration Scheme 57
3.4 Multi-Mode Processing Modules 58
3.4.1 Fading Channel Weighting Generator 59
3.4.2 Interpolator 60
3.4.3 Register Bank 60
3.4.4 Multipath Fading Signal Generator 60
3.5 Comparisons between Experimental Results and Empirical Meas-urements 62
3.6 Summary 67
Appendix 3 68
Appendix 3.A A reconfiguration control algorithm of SDR channel simulator 68
Appendix 3.B Derivations of two dimensional discrete channel fre-quency responses 69
Chapter 4 Implementation of SDR Digital Beamformer for Mi-cro-Satellite SAR 71
4.1 Introduction 71
4.2 Structure of SDR DBF 73
4.3 Implementation of the Multi-Mode DBF Processing Modules on the FPGA Processor 77
4.4 Experimental Results 83
4.6 Summary 86
Appendix 4 87
Appendix 4.A Reconfiguration control algorithm 87
Chapter 5 Realization of the MC-DSSS Phased Array Radar Based on SDR Structure 89
5.1 Introduction 89
5.2 Principles of MC-DSSS Radar 91
5.3 Design of the FFT-based DBF 96
5.4 Implementation of SDR platform 101
5.5 Experimental Results 108
5.6 Summary 114
Chapter 6 Conclusions 116
6.1 Summary of Dissertation 116
6.2 Future Work 117
Reference 118
Vita 124
Publication List 125
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