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研究生:廖勇政
研究生(外文):Yung-Cheng Liao
論文名稱:應用於UWB接收機射頻前端積體電路之研製
論文名稱(外文):The Design and Implementation of RF Receiver Integrated Circuit for UWB Applications
指導教授:楊正任
指導教授(外文):Jeng-Rern Yang
學位類別:碩士
校院名稱:元智大學
系所名稱:通訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:87
中文關鍵詞:超寬頻接收機低雜訊放大器混頻器
外文關鍵詞:UWBReceiverLNAMixer
相關次數:
  • 被引用被引用:3
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本論文提出一全積體化之UWB 接收機射頻前端積體電路之研製,使用TSMC 0.18 μm 1P6M CMOS製程實現,可應用於UWB低雜訊放大器及混頻器之設計。UWB系統是一無線網路技術,能在低功率消耗之條件下,於短距離內達到高速無線寬頻傳輸;本低雜訊放大器設計符合UWB(IEEE 802.15.3a)從3.1到10.6 GHz之頻段。並透過國家晶片系統設計中心 (CIC) 之協助,完成此晶片之製作。由於傳統設計寬頻放大器大多使用晶片面積或功率消耗較大的架構,因此本論文以CG方式作為RF輸入匹配網路,減少使用多電感作為寬頻匹配而造成晶片整體面積較大;因使用單一電感做匹配,因此縮小了晶片面積,此晶片面積大小為0.5mm2。另外將此匹配網路配合RC回授電路及中間級電感的疊接放大級,設計出3.1~10.6GHz低雜訊放大器,在整個寬頻帶中,可獲得較佳的增益平坦度。
另外提出使用CG之匹配網路作為雙輸入之方式,設計一含3~11GHz頻段之寬頻混頻器;因使用單一電感作為匹配,因此可縮小晶片面積。經模擬結果,其操作頻率為3~11GHz,轉換增益大於6dB,雜訊指數為5.9~8.2dB,P1dB為-19.5dB,IIP3為-9.5~-8.0dB,消耗功率14.7mW。
This thesis proposed for the developments of receiver RFICs for Ultra-wide-band UWB system with the TSMC 0.18um 1P6M CMOS process. The designed ICs for the low noise amplifier (LNA), down-convert mixer applications. UWB systems are an emerging wireless technology capable of transmitting data over a wide frequency band for short ranges with low power and even higher data rate. The allocated band of UWB (IEEE 802.15.3a) is between 3.1–10.6 GHz. The designed is also supported by the chip implementation center (CIC). Due to the traditional designs of UWB LNAs usually consume plenty of chip size and power, thus we proposed a input matching network that with common-gate and utilizes an inductor in it, so it can reduce the utilization of chip area. The total chip size with pads was 0.5mm2. In addition, the matching network cooperates with RC feedback circuit and a cascade amplifier with an inter-stage inductor. In the design of 3-6 GHz low noise amplifier, the designed in-band gain of UWB mode can be flat.
Over and above, we proposed a mixer with a common-gate (CG) matching network. The operated frequency was 3-11GHz; Due to the matching structure only use single spiral inductor, so the utilization of chip area can be reduced. The simulation performances are as follows: the bandwidth 3 ~ 11 GHz, gain is above 6 dB, noise figure in 5.9~8.2 dB, P1dB gain-compression point in ????5 dBm, and the input third- intercept-point in about -9.5~8.0 dBm, the dissipated power was 14.7mW.
書名頁 i
論文口試委員審定書 ii
授權書 iii
中文摘要 iv
英文摘要 v
誌謝 vi
目錄 vii
表目錄 x
圖目錄 xi

第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 章節概述 3
第二章 接收機系統架構 5
2.1 接收機基本概念 6
2.2 超外差接收機架構 8
2.2.1 鏡像頻率之影響 9
2.2.2 半中頻之影響 11
2.2.3 中頻頻率之選擇 12
2.2.4 雙中頻架構 14
2.3 直接降頻接收機架構 16
2.3.1 直流偏移 17
2.3.2 I/Q信號的不匹配 18
2.3.3 偶次階失真 19
2.3.4 顫動雜訊 20
2.3.5本地信號洩漏 21
2.4 鏡像消除接收機架構 21
2.4.1 Hartley架構 21
2.4.2 Weaver架構 25
2.5 數位中頻接收機 26
第三章 CMOS UWB低雜訊放大器 28
3.1 簡介 28
3.2 使用回授電路之CMOS UWB低雜訊放大器的設計 30
3.2.1 電路架構 30
3.2.2 設計原理與流程 31
3.2.3 電路模擬結果與討論 38
3.2.4 量測結果分析 44
3.3結論 50
第四章 UWB混頻器之設計 52
4.1 簡介 52
4.2 混頻器基本概念 52
4.2.1 ㄧ般考量 52
4.2.2 混頻器的規格參數 53
4.2.3 混頻器的種類 61
4.2.4 主動式混頻器架構 63
4.3 UWB混頻器之設計 65
4.3.1 雙平衡混頻器操作原理 65
4.3.2 電路架構 68
4.4 電路模擬結果 71
4.5 結論 76
第五章 UWB接收機射頻前端積體電路設計 77
5.1電路架構 77
5.2電路模擬結果 78
5.3結論 83
第六章 結論 84
參考文獻 85
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