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研究生:吳弘成
研究生(外文):Hung-Cheng Wu
論文名稱:MIMO-DSRC傳接機於FPGA之實現研究
論文名稱(外文):Realization of MIMO-DSRC transceiver using FPGA
指導教授:馬杰馬杰引用關係
指導教授(外文):Chieh Ma
學位類別:碩士
校院名稱:元智大學
系所名稱:通訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:94
中文關鍵詞:傳接機實現
外文關鍵詞:MIMODSRCFPGA
相關次數:
  • 被引用被引用:1
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多輸入多輸出(Multiple Input Multiple Output,MIMO)特定短程通訊(Dedicated Short Range Communications,DSRC)傳接機,實現於軟體無線電(Software Defined Radio,SDR)處理平台,可選擇八種不同資料率與四種通道車速的傳輸;藉由MIMO-OFDM技術,可進一步降低位元錯誤率並提高位元傳輸率;軟體無線電平台是使用FPGA處理器進行硬體重新配置,相較於DSP處理器下,可加快處理速度,以符合IEEE 802.11p標準。
本篇論文根據IEEE 802.11p標準設計MIMO-DSRC傳接機,可透過SDR處理平台對硬體進行重新配置,研究項目包含:(1) 結合FPGA處理器與DSP信號處理器實現SDR MIMO-DSRC傳接機;(2) 應用Cordic演算法,設計通道估測與補償之電路模組;(3)以IEEE 802.11p DSRC通道,進行MIMO-DSRC系統性能測試;(4)圖形使用者介面操作SDR處理平台。
Multiple Input Multiple Output Dedicated Short Range Communications (MIMO-DSRC) transceiver is implemented in a software defined radio (SDR) platform which consists of eight different data transmission rates and four vehicle channel types. The MIMO-OFDM technology is used to reduce the bit error rate (BER) and to increase the bit transmission rate. The SDR platform is realized with the FPGA processor to reconfigure the hardware module and to increase the processing speed.
In this thesis, MIMO-DSRC transceiver is designed in accordance with IEEE 802.11p standard. The research items include:

(1) Realization of DSRC base band SDR platform on FPGA and DSP processors.
(2) Application of the Cordic(Coordinate Rotation Digital Computer) algorithm for designing the channel estimation and compensation circuit module.
(3) Test of the BER performance of MIMO-DSRC transceiver using IEEE 802.11p channel model.
(4) Demonstration the function of the SDR platform using Graphical User Interface(GUI).
1. 緒論 1
1.1研究背景與動機 1
1.2研究方法 2
1.3論文架構 3

2. DSRC通訊系統傳接機演算法原理 4
2.1 IEEE 802.11p DSRC標準簡介 4
2.2 DSRC系統之訊框結構 4
2.3 DSRC系統發射機架構 10
2.4 DSRC系統接收機架構 15

3. MIMO-DSRC傳接機於FPGA之實現 25
3.1 FPGA與TI C6x數位訊號處理器硬體架構 25
3.2 MIMO-DSRC軟體無線電平台 29
3.3 MIMO-DSRC 34
3.4 SFBC-DSRC 35
3.5 MIMO-DSRC傳接機於FPGA之實現 45

4. 接收機之載波頻率與通道估測補償 63
4.1載波頻率估測與補償電路模組 63
4.2長訓練符元通道估測電路模組 65
4.3領航訊號通道估測電路模組 66
4.4 CORDIC演算法 67
4.5電路模組性能測試結果 78

5. MIMO-DSRC傳接機性能測試結果 84
5.1 MIMO-DSRC傳接機平台測試架構 84
5.2 測試結果 85

6. 結論 91

參考文獻 92
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