臺灣博碩士論文加值系統

智慧型系統以及系統上的軟體在近幾年有大幅度的需求以及成長，而user experience為軟體的一大指標。好的user experience除了系統架構外，往往還需要有好的使用者介面來增加系統操作的便利性。為了讓使用者介面能更直覺化以及美觀，非常多的設計導入了3D元件，使得界面更為便利、美觀以及為自家產品樹立了個人風格以和競爭對手做一個區隔。然而，並非所有的智慧型裝置都擁有能夠順暢運行3D計算的硬體平台。許多較為低階或者低功耗的平台在硬體上的缺乏或不足( 無GPU以及使用較低時脈的CPU )造成3D運算為系統帶來龐大的負擔。此論文提出利用DSP來輔助進行3D運算。雖然DSP相較於GPU不利於3D運算，可是低階平台並不著重於高負載的3D運算，例如遊戲。使用DSP來進行運算一來可降低CPU負載，使系統運行更順暢。二來DSP運算更省電，如此一來可延長系統待命時間。為了使DSP能達到最好的運算效能，本論文使用了以下兩個方法：1、Dynamic Code Generation的方法於run-time時產生最佳化後的DSP binary來進行3D計算。2、Parallel execution讓ARM與DSP同時進行來獲取最大效益。本論文實作展現了利用DSP輔助3D運算的可行性。

There has been a great expansion on the use and requirement of intelligent systems on mobile/multi-media devices. End users takes a great concern on how good is the user experience for the product. Not only does well designed system architecture contribute to good user experience, a user-friendly UI is also important. In recent designs, lots of 3D elements ( ex : Open GL ) has been merged into the UI systems. With these designs, UI has become more pleasant, easy to use for users, and to make distinctions between products. Smooth execution of 3D graphic needs base amount of computing resources, which might not be enough in low-end or low-power devices. Low end/power devices usually doesn't have GPU or fast CPU to perform 3D computation. Based on this reason, this paper propose a method which use digital signal processor ( DSP ) to accelerate 3D computation. Although DSP can't reach the level of GPU in graphic computation, our main target is not computing complex 3D scene but simple model ( ex : UI, light-weight AP ). Using DSP instead of GPU could benefit platform power consumption and hardware cost. On the other hand, DSP could share computation loading from CPU on GPU-lacked platform.This paper proposed two approaches for using DSP to accelerate 3D computation. 1 : Dynamic Code Generation. System generate binary code for DSP at run-time, which the binary code is highly optimized. 2 : Parallel execution of ARM and DSP. On low end/power devices, single unit could have limited resource. Combining two unit could produce better resource.

1.簡介 1
2.動機 3
3.相關研究 6
3.1二進制碼轉譯(Binary Translation) 6
3.1.1 IA-32 Execution Layer 7
3.1.2 Transmeta Crusoe 9
3.2 3D繪圖硬體與軟體介紹 11
3.2.1圖形處理器( GPU )架構 11
3.2.2 3D軟體繪圖函式庫 14
3.3 數位信號處理器( DSP ) 14
3.3.1 DSP架構與相關應用 14
3.3.2 PAC DSP 16
4. 系統架構與設計 19
4.1 平台簡介 19
4.1.1 Android平台簡介 19
4.1.2 Open GL|ES繪圖流程 20
4.1.3 PAC DSP平台特性與相關功能 21
4.2 繪圖函式庫效能測量 23
4.3 Android上Open GL|ES最佳化方法 25
4.4 PAC架構下之動態二進制碼產生器設計 33
4.4.1 PAC-RISC GENERATOR 34
4.4.2 PAC-RISC Scheduler 36
4.4.3 Virtual Register生命週期 42
4.5 ARM與PAC之平行化執行 42
5. 實驗 44
6. 結論 47
參考文獻 48

[1] L. Baraz et al., "IA-32 Execution Layer: A Two-Phase Dynamic Translator Designed to Support IA-32 Applications on Itanium-Based Systems," Proc. 36th Ann. IEEE/ACM Int’l Symp. Microarchitecture, IEEE CS Press, 2003, pp. 191-204.

[2] Alexander Klaiber, "The Technology Behind the Crusoe Processors," White Paper, http://www.transmeta.com/pdf/white_papers/paper_aklaiber_19jan00.pdf, Jan. 2000.

[3] James C. Dehnert, et al., "The Transmeta Code Morphing Software: Using Speculation, Recovery, and Adaptive Retranslation to Address Real-Life Challenges," Proceedings of the First Annual IEEE/ACM International Symposium on Code Generation and Optimization, March 2003, pp.15-24

[4] Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, and Sumedh Sathaye, "Dynamic Binary Translation and Optimization," IEEE Trans. on Computers 50 (6), June 2001, pp. 529-548.

[5] Kemal Ebcioglu and Erik R. Altman, "DAISY: Dynamic Compilation for 100% Architectural Compatibility," Proc. of the 24th Annual Int’l Symp. on Computer Architecture, June 1997, pp. 26-37

[6] F. Bellard. "QEMU, a Fast and Portable Dynamic Translator," Proceedings of the USENIX Annual Technical Conference, FREENIX Track, pages 41–46, 2005.

[7] VMware, http://www.vmware.com/.

[8] E. R. Altman, D. Kaeli, and Y. Sheffer, "Welcome to the Opportunities of Binary Translation," IEEE Computer, March 2000, pp. 40-45.

[9] Java Virtual Machine, http://java.sun.com/.

[10] Khronos Open GL, http://www.khronos.org/opengl/.

[11] Microsoft Directx 3D, http://www.microsoft.com/download/en/details.aspx?displaylang=en&id=2858.
[12] Khronos Open GL|ES, http://www.khronos.org/opengles/.

[13] Windows Advanced Rasterization Platform (WARP), http://msdn.microsoft.com/en-us/library/gg615082.aspx.

[14] J. Nickolls, I. Buck, K. Skadron, and M. Garland, "Scalable Parallel Programming with CUDA," ACM Queue, vol. 6, no. 2, Mar./Apr. 2008, pp. 40-53.

[15] E. Lindholm, J. Nickolls, S. Oberman, J. Montrym, "NVIDIA Tesla: A uni_ed graphics
and computing architecture,” IEEE Micro 28 (2) (2008) 39.55.

[16] Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim, "A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache," IEEE Trans. on VLSI Volume: 19, Issue:4, April 2011, pp. 525-537

[17] Yovits, Marshall C, “Advances in computers,” Academic Press. pp. 105–107.

[18] Liptak, Béla G. (2006), "Instrument Engineers' Handbook: Process control and optimization," 2, CRC Press, pp. 11–12.

[19] R. Bhargava et al, "EvaluatingMMX Technology Using DSPand Multimedia Applications," In MICRO-31, Dec 1998.

[20] Texas Instrument( TI ) DSP information, http://focus.ti.com/dsp/docs/dsphome.tsp?sectionId=46&DCMP=TIHeaderTracking&HQS=Other+OT+hdr_p_dsp.

[21] Chang, C.-W., Lin, T.-J., Wu, C.-J., Lee, J.-K., Chu, Y.-H., & Wu, A.-Y. "Parallel Architecture Core (PAC)—the first MulticoreApplication processor SoC in Taiwan part I: Hardware architecture & software development tools," Journal of Signal Processing Systems, Springer Science+Business Media, LLC Mar. 2010.

[22] Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Jenq-Kuen Lee, "Compiler Supports and Optimizations for PAC VLIW DSP Processors," Languages and Compilers for Parallel Computing, 2005.

[23] Wu, C. J., Chen, S. Y., & Lee, J. K., "Copy propagation optimizations for VLIW DSP processors with distributed register files," Languages and Compilers for Parallel Computing (LNCS 4382), pp.251–266, Jun. 2007.

[24] Yung-Chia Lin, Yi-Ping You, Jenq-Kuen Lee, "Register Allocation for VLIW DSP Processors with Irregular Register Files," Proceedings of the 12th Workshop on Compilers for Parallel Computers (CPC 2006), Jan 9–11 2006.

[25] Lu, C. H., Lin, Y. J., You, Y. P., & Lee, J. K. (2009). LC-GRFA:global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. Concurrency and Computation: Practice and Experience, 21, 101–114.