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研究生:郭士齊
研究生(外文):Shih-Chi Kuo
論文名稱:適用於可變延遲處理器的多週期資料路徑合成方法
論文名稱(外文):Synthesis of Multi-Cycle Datapath for Variable-latency Processor
指導教授:陳添福陳添福引用關係
指導教授(外文):Tien-Fu Chen
學位類別:碩士
校院名稱:國立中正大學
系所名稱:資訊工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:46
中文關鍵詞:多週期電路合成可變異處理器
外文關鍵詞:processormulti-cyclevariable-latencysynthesis
相關次數:
  • 被引用被引用:0
  • 點閱點閱:269
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  • 下載下載:10
  • 收藏至我的研究室書目清單書目收藏:0
降低系統電壓是減少電量消耗最直接且最有效的方法,而在低電壓的環境上,半導體電路的系統變異影響卻是更大,使得傳統用於滿足最糟情況的設計變得效能低落。因此有可變延遲之設計提出,使得較慢且較少發之情況得以執行較長的時間。於本篇論文,我們提出一種適用於可變延遲處理器的多模式多週期資料路徑,其執行週期會隨製程技術(P)、供電電壓(V)、溫度(T)以及資料樣式(D)而改變。我們更進一步提出一個自動化合成多週期資料路徑的方法。該合成方法可根據不同控制訊號及多種工作環境的資訊,自動將一個單週期電路轉成多週期電路。順道一提,我們利用類似razor的偵錯器收集錯誤率來達到模式切換無誤。於此我們實作一個可變延遲的RISC五級管線處理器(UniRISC)來呈現本論文所提方法的功效。
Lowering supply voltages is the most straightforward and effective way to reduce power consumption. However, design variations of CMOS circuits become much more significant under low supply voltage, which makes conventional worst-case designs very inefficient. Therefore, variable-latency designs were proposed, of which the slower but infrequent cases are executed with longer latencies. In this thesis, a multi-mode and multi-cycle datapath has been introduced for variable-latency processors, which changes the execution cycles under the variations on the process technology (P), the supply voltage (V), the temperature (T), and even the data patterns (D). Moreover, the automatic synthesis of multi-cycle datapaths has been proposed, which transforms a single-cycle RTL description into a multi-cycle one depending on different control words and various working conditions. By the way, the mode change is accomplished with the error rate collected from Razor-like detectors. A variable-latency RISC core with 5-stage pipelined datapath (Uni-RISC) has been implemented to demonstrate the effectiveness of our proposed methodology.
Chapter 1 Introduction
1.1 Motivation
1.2 Main contribution
1.3 Thesis organization
Chapter 2 Background
2.1 Variations
2.2 Related works
Chapter 3 Synthesis of Multi-Cycle Datapaths
3.1 Variable-latency processors
3.2 Multi-cycle datapaths design
3.3 Optimization and control generation
Chapter 4 Experimental Results
4.1 Experiment setup
4.2 Performance evaluation
4.3 Cost estimation
Chapter 5 Conclusion and Future Works
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